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| part number 440GRX revision 1.08 ? october 15, 2007 amcc proprietary 1 440GRX powerpc 440GRX embedded processor preliminary data sheet features ?powerpc ? 440 processor operating up to 667mhz with 32kb i-cache and d-cache with parity checking. ? 16kb of on-chip sram. ? selectable processor:bus cl ock ratios of n:1, n:2. ? dual bridged processor local buses (plbs) with 64- and 128-bit widths. ? double data rate 2/1 (ddr2/1) synchronous dram (sdram) interface operating up to 166mhz (333 mhz data transfer rate) with optional ecc. ? dma support for external peripherals, internal uart and memory. ? pci v2.2 interface (3.3v on ly). thirty-two bits at up to 66mhz. ? programmable interrupt controller supports interrupts from a variety of sources. ? programmable general purpose timers (gpt). ? two ethernet 10/100/1000mbps half- or full- duplex interfaces. operational modes supported are with packet reject, jumbo frames, and interrupt coalescing. ? up to four serial ports (16750 compatible uart). ? external peripheral bus (32-bit data) for up to six devices with external mastering. ? two iic interfaces (one with bootstrap capability). ? nand flash interface. ? spi interface. ? general purpose i/o (gpio) interface. ? jtag interface for board level testing. ? boot from pci memory, nor flash on the external peripheral bus, or nand flash on the nand flash interface. ? optional security feature (ppc440GRX-s). ? available in rohs comp liant, lead-free package. description designed specifically to address high-end embedded applications, the powerpc 440GRX (ppc440GRX) provides a high-performance, low-power solution that interfaces to a wide range of peripherals and incorporates on-chip power management features. this chip contains a high-performance risc processor, on-chip sram, ddr2/1 sdram controller, pci bus interface, control for external rom and peripherals, dma with scatter/gather support, ethernet ports, serial ports, iic interfaces, spi interface, nand flash interface, an optional security feature (ppc440GRX-a), and general purpose i/o. technology: cmos cu-11, 0.13 m. package: 35mm, 680-ball thermally enhanced plastic ball grid array (te-pbga). rohs compliant package available. typical power (estimated): approximately 3.3 w at 533mhz. supply voltages required: 3.3v, 2.5v, 1.8v (ddr2) or 2.5v (ddr1), 1.5v.
440GRX ? ppc440GRX embedded processor preliminary data sheet 2 amcc proprietary revision 1.08 ? october 15, 2007 contents ordering and pvr information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 address maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 powerpc 440 processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 sram controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 internal buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 security function (optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 kasumi algorithm (optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 pci controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 ddr2/1 sdram memory controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 external peripheral bus controller (ebc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 ethernet controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 dma-to-plb3 (64-bit) controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 serial ports (uart) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 iic bus controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 serial peripheral controller (spi/scp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 nand flash controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 general purpose timers (gpt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 general purpose io (gpio) controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 universal interrupt controller (uic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 jtag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 package diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 signal lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 device characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 spread spectrum clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 i/o specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 ddr2/1 sdram i/o specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 ddr sdram write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 ddr sdram read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 strapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 serial eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 440GRX ? ppc440GRX embedded processor revision 1.08 ? october 15, 2007 amcc proprietary 3 preliminary data sheet figures figure 1. order part number key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. ppc440GRX functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. 35mm, 680-ball te-pbga package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 4. overshoot waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 5. timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 6. input setup and hold waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 7. output delay and float timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 8. input setup and hold waveform for rgmii signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 9. output delay and hold timing wave form for rgmii signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 10. ddr sdram simulation signal termination model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 11. ddr sdram write cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 12. ddr sdram dqs read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 tables table 1. system memory address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 2. dcr address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 3. recommended reflow soldering profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 4. jedec moisture sensitivity level and ball composition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 5. signals listed alphabetically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 6. signals listed by ball assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 7. pin summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 8. reserved pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 9. signal functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 10. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 11. recommended dc operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 12. input capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 13. overshoot and undershoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 14. typical dc power supply requirem ents using ddr2 memory . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 15. typical dc power supply requirem ents using ddr1 memory . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 16. v dd supply power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 17. dc power supply loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 18. package thermal specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 19. clocking specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 20. peripheral interface clock timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 21. i/o specifications?all speeds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 22. i/o specifications?400mhz to 667mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 23. ddr sdram output driver specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 24. ddr sdram write operatio n conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 25. i/o timing?ddr sdram t ds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 26. i/o timing?ddr sdram t sk , t sa , and t ha . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 440GRX ? ppc440GRX embedded processor preliminary data sheet 4 amcc proprietary revision 1.08 ? october 15, 2007 table 27. i/o timing?ddr sdram t sd and t hd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 28. strapping pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 440GRX ? ppc440GRX embedded processor revision 1.08 ? october 15, 2007 amcc proprietary 5 preliminary data sheet ordering and pvr information for information on the availability of the following parts, contact your lo cal amcc sales office. for additional information on the part number structure see figure 1 . each part number contains a revision code. this is the die mask revision number and is included in the part number for identification purposes only. the pvr (processor version register) and the jtag id register are software accessible (read-only) and contain information that uniquely identi fies the part. refer to the ppc440GRX user?s manual for details on accessing these registers. figure 1. order part number key product name order part number (see notes ) package revision level pvr value jtag id ppc440GRX ppc440GRX-spafffts 35mm, 680 te-pbga a 0x216218d0 0x0440f1e1 ppc440GRX ppc440GRX-npafffts 35mm, 680 te-pbga a 0x216218d4 0x0440f1e1 notes: characters following the dash (-): 1. s = security feature present, n = security feature not present 2. p = package type: u = lead-free (rohs compliant), t = contains lead 3. a = chip revision level a 4. fff = processor frequency: 400 = 400mhz, 533 = 533mhz, 667 = 667mhz 5. t = case temperature range of ? 40 c to +100 c 6. s = shipping package type: z = tape-and-reel. blank = tray amcc part number ppc440GRX-sua667tz package processor frequency case temperature range revision level shipping package security feature note: the example p/n above contains the security feature, is lead-free, is capable of running at 667 mhz, and is shipped in tape-and-reel packaging. 440GRX ? ppc440GRX embedded processor preliminary data sheet 6 amcc proprietary revision 1.08 ? october 15, 2007 block diagram figure 2. ppc440GRX functional block diagram the ppc440GRX is a system on a chip (soc) using ibm coreconnect bus ? architecture. processor dcr bus 32kb on-chip peripheral bus (opb 0) gpio iic uart plb (plb4?128 bits) ddr2/1 external peripheral controller controller clock control, reset power mgmt jtag trace timers mmu - 30-bit addr - 32/16-bit data - 14-bit addr - 64/32-bit data nand flash controller uic i-cache 32kb d-cache ppc440 pci bridge x2 x4 mal ethernet x2 dcrs gpt zmii 83mhz max 10/100/1000 66mhz max 333mhz max plb (plb3?64 bits) plb bridge spi - 32 bits - 6 devices external bsc 10 dma controller opb bridge interrupts security sram 16kb (x-bar) (optional) data rate rgmii sdram dma controller 440GRX ? ppc440GRX embedded processor revision 1.08 ? october 15, 2007 amcc proprietary 7 preliminary data sheet address maps the ppc440GRX incorporates two address maps. the first is a fixed processor system memory address map. this address map defines the possible contents of vari ous address regions which the processor can access. the second is the dcr address map for devi ce configuration registers (dcrs). the dcrs are accessed by software running on the ppc440GRX processor through the use of mtdcr and mfdcr instructions. table 1. system memory address map (sheet 1 of 2) function sub function start address end address size total system memory address space 0 0000 0000 1 ffff ffff 8gb local memory ddr sdram 0 0000 0000 0 7fff ffff 2gb reserved 0 8000 0000 0 e000 ffff on-chip memory sram 0 e001 0000 0 e001 3fff 16kb reserved 0 e001 4000 0 e00f ffff security (ppc440GRX-s) security function 0 e010 0000 0 e017 ffff 512kb kasumi algorithm 0 e018 0000 0 e018 07ff 2kb reserved 0 e018 0800 1 7fff ffff pci 1 memory 1 8000 0000 1 bfff ffff 1gb ebc 1 controller 1 c000 0000 1 dfff ffff 512mb reserved 1 e000 0000 1 e7ff ffff pci 1 i/o 1 e800 0000 1 e800 ffff 64kb reserved 1 e801 0000 1e87f ffff i/o 1 e880 0000 1 ebff ffff 56mb reserved 1 ec00 0000 1 eebf ffff configuration registers 1 eec0 0000 1 eec0 0007 8b reserved 1 eec0 0008 1 eecf ffff interrupt ack/special cycle 1 eed0 0000 1 eed0 0003 4b reserved 1 eed0 0004 1 ef3f ffff local configuration registers 1 ef40 0000 1 ef40 003f 64b reserved 1 ef40 0040 1 ef4f ffff 440GRX ? ppc440GRX embedded processor preliminary data sheet 8 amcc proprietary revision 1.08 ? october 15, 2007 internal peripherals reserved 1 ef50 0000 1 ef5f ffff general purpose timer 1 ef60 0000 1 ef60 01ff 512b reserved 1 ef60 0200 1 ef60 02ff uart0 1 ef60 0300 1 ef60 0307 8b reserved 1 ef60 0308 1 ef60 03ff uart1 1 ef60 0400 1 ef60 0407 8b reserved 1 ef60 0408 1 ef60 04ff uart2 1 ef60 0500 1 ef60 0507 8b reserved 1 ef60 0508 1 ef60 05ff uart3 1 ef60 0600 1 ef60 0607 8b reserved 1 ef60 0608 1 ef60 06ff iic0 1 ef60 0700 1 ef60 071f 32b reserved 1 ef60 0720 1 ef60 07ff iic1 1 ef60 0800 1 ef60 081f 32b reserved 1 ef60 0820 1 ef60 08ff spi 1 ef60 0900 1 ef60 0906 6b reserved 1 ef60 0907 1 ef60 09ff opb0 arbiter 1 ef60 0a00 1 ef60 0a3f 64b reserved 1 ef60 0a40 1 ef60 0aff gpio0 controller 1 ef60 0b00 1 ef60 0b7f 128b reserved 1 ef60 0b80 1 ef60 0bff gpio1 controller 1 ef60 0c00 1 ef60 0c7f 128b reserved 1 ef60 0c80 1 ef60 0cff ethernet phy zmii 1 ef60 0d00 1 ef60 0d0f 16b reserved 1 ef60 0d10 1 ef60 0dff ethernet 0 controller 1 ef60 0e00 1 ef60 0e77 120b reserved 1 ef60 0e78 1 ef60 0eff ethernet 1 controller 1 ef60 0f00 1 ef60 0f77 120b reserved 1 ef60 0f78 1 ef60 0fff ethernet phy rgmii 1 ef60 1000 1 ef60 1103 264b reserved 1 ef60 1080 1 efff ffff ebc 1 1 f000 0000 1 ffdf ffff 254mb boot space ebc bank 0 or pci 1 ffe0 0000 1 ffff ffff 2mb notes: 1. ebc and pci are relocatable, but this map reflects the s uggested configuration. table 1. system memory address map (sheet 2 of 2) function sub function start address end address size 440GRX ? ppc440GRX embedded processor revision 1.08 ? october 15, 2007 amcc proprietary 9 preliminary data sheet table 2. dcr address map function start address end address size total dcr address space 1 000 3ff 1kw (4kb) 1 by function: reserved 000 00b clocking power on reset (cpr0) 00c 00d 2w system dcrs (sdr0) 00e 00f 2w memory controller (sdram0) 010 011 2w external bus controller (ebc0) 012 013 2w reserved 014 01f plb4-to-plb3 bridge out 020 02f 16w plb3-to-plb4 bridge in 030 03f 16w reserved 040 06f plb3 arbiter 070 07f 16w plb4 arbiter 080 08f 16w plb3-to-opb0 bridge 090 09f 16w reserved 0a0 0af power management 0b0 0b7 8w reserved 0b8 0bf interrupt controller 0 0c0 0cf 16w interrupt controller 1 0d0 0df 16w interrupt controller 2 0e0 0ef 16w power management 1 0f0 0f7 8w reserved 0f8 0ff dma-to-plb3 controller 100 13f 64w reserved 140 17f ethernet mal 180 1ff 128w reserved 200 2ff dma-to-plb4 controller 300 33f 64w reserved 340 37f on chip memory (sram controller) 380 38f 16w reserved 390 3ff notes: 1. dcr addresses are 10 bits (1024 or 1k unique addresses). each unique address represents a single 32-bit (word) register. one kiloword (1024w) equals 4kb (4096 b). 440GRX ? ppc440GRX embedded processor preliminary data sheet 10 amcc proprietary revision 1.08 ? october 15, 2007 powerpc 440 processor the powerpc 440 processor is designed for high-end applications: raid contro llers, san, iscsi, routers, switches, printers, set- top boxes, etc. it implements the book e po werpc embedded architecture and uses the 128-bit version of ibm?s on-chip coreconnect bus architecture. features include: ? up to 667mhz operation ? powerpc book e architecture ? 32kb i-cache, 32kb d-cache ? utlb word wide parity on data and tag address parity with exception force ? three logical regions in d-cache: locked, transient, normal ? d-cache full line flush capability ? 41-bit virtual address, 36-bit (64gb) physical address ? superscalar, out-of-order execution ? 7-stage pipeline ? 3 execution pipelines ? dynamic branch prediction ? memory management unit ? 64-entry, full associative, unified tlb with optional parity ? separate instruction and data micro-tlbs ? storage attributes for write-through, cache- inhibited, guarded, and big or little endian ? debug facilities ? multiple instruction and data range breakpoints ? data value compare ? single step, branch, and trap events ? non-invasive real-time trace interface ? 24 dsp instructions ? single cycle multiply and multiply-accumulate ? 32 x 32 integer multiply ? 16 x 16 -> 32-bit mac sram controller the internal sram controller (isc) supports the following features: ? one bank (bank 0) of 16kb configurable as 4kb, 8kb or 16kb (128 bits wide) ? 128-bit slave attachment addressable by any plb master ? transfers by plb slave cycles: ? single-beat read and write (1 to 8 bytes for 64-bit masters, 1 to 16 bytes for 128-bit masters) ? 4-word line read and write ? 8-word line read and write ? double word read and write bursts for 64-bit masters ? quadword read and write bursts for 128-bit masters ? slave-terminated double word a nd quadword fixed length bursts ? master-terminated variable length bursts ? guarded memory access on 4 kb boundaries ? data parity checking ? data transfers occur at plb bus speeds. ? power management 440GRX ? ppc440GRX embedded processor revision 1.08 ? october 15, 2007 amcc proprietary 11 preliminary data sheet internal buses the powerpc 440GRX features four standard internal buses: two processor local buses (plbs), one on-chip peripheral buses (opbs), and the device control regist er bus (dcr). the high performance, high bandwidth cores such as the powerpc 440 processor, the ddr s dram memory controller, and the pci bridge connect to the plbs. opb0 hosts lower data rate peripherals. the daisy-chained dcr provides a lower bandwidth path for passing status and control information between the processor and t he other on-chip cores. features include: ? plb4 (128-bit) ? 128-bit implementation of the plb architecture ? separate and simultaneous read and write data paths ? 36-bit address ? simultaneous control, address, and data phases ? four levels of pipelining ? byte-enable capa bility supporting unaligned transfers ? 32- and 64-byte burst transfers ? 166mhz, maximum 5.3gb/s (simultaneous read and write) ? processor:bus clock ratios of n:1 and n:2 ? plb3 (64-bit) ? 64-bit implementation of the plb architecture ? 32-bit address ? 166mhz (1:1 ratio with plb4), maximum 1.3gb/s (no simultaneous read and write) ?opbs (opb0) ? 32-bit data path ? 32-bit address ?83mhz ? dcr ? 32-bit data path ? 10-bit address security funct ion (optional) the built-in security function (ppc440GRX -s only) is a cryptographic engine at tached to the 128-bit plb with built- in dma and interrupt controllers. features include: ? federal information processing standard (fips) 140-2 design ? support for an unlimited number of security associations (sa) ? different sa formats for each supported protocol (ipsec/ssl/tls/srtp) ? internet protocol security (ipsec) features ? full packet tran sforms (esp & ah) ? complete header and trailer processing (ipv4 and ipv6) ? multi-mode automatic padding ? "mutable bit" handler for ah, including ipv4 option and ipv6 extension headers ? secure socket layer (ssl) and transport layer security (tls) features ? packet transforms ? one-pass hash-then-encrypt for ssl and tls packet transforms for inbound packet using stream cipher ? secure real-time protocol (srtp) features ? packet transforms ? roc removal and tag insertion ? variable bypass offset of header length per packet ? ipsec/ssl security acceleration engine ? des, 3des, aes, arc-4 encryption ? md-5, sha-1 hashing, hmac encryp t-hash and hash-decrypt, and kasumi 440GRX ? ppc440GRX embedded processor preliminary data sheet 12 amcc proprietary revision 1.08 ? october 15, 2007 ? public key acceleration for rsa, dsa and diffie-hellman ? true or pseudo random number generators ? non-deterministic true random numbers ? pseudo random numbers with lengths of 8b or 16b ? ansi x9.17 annex c compliant using a des algorithm ? interrupt controller ? fifteen programmable, maskable interrupts ? initiate commands via an input interrupt ? sixteen programmable interrupts indicating completion of certain operations ? all interrupts mapped to one level- or edge-sensitive programmable interrupt output ? dma controller ? autonomous, 4-channel ? 1024-words (32 bits/word) per dma transfer ? scatter/gather capability wit h byte aligned addressing kasumi algorithm (optional) ? key scheduling hardware ? f8 and f9 algorithm support ? automatic data padding mechanism for f9 algorithm ? kasumi encryption an d decryption modes ? 32-bit slave interface ? fully synchronous to plb clock pci controller the pci interface allows connection of pci devices to th e powerpc processor and local memory. this interface is designed to version 2.2 of the pci specif ication and supports 32- bit pci devices. reference specifications: ? powerpc coreconnect bus (plb) specification version 3.1 ? pci specification version 2.2 ? pci bus power management interface specification version 1.1 features include: ?pci 2.2 ? frequency to 66mhz ? 32-bit bus ? pci host bus bridge or an adapter device's pci interface ? internal pci arbitration function, supporting up to six ex ternal devices, that can be disabled for use with an external arbiter ? support for message signaled interrupts ? simple message passing capability ? asynchronous to the plb ? pci power management 1.1 ? pci register set addressable both from on-chip processor and pci device sides ? ability to boot from pci bus memory ? error tracking/status ? supports initiation of transfers of the following types: ? single beat i/o reads and writes ? single beat and burst memory reads and writes ? single beat configuration reads and writes (type 0 and type 1) ? single beat special cycles 440GRX ? ppc440GRX embedded processor revision 1.08 ? october 15, 2007 amcc proprietary 13 preliminary data sheet ddr2/1 sdram memory controller the double data rate 2/1 (ddr2/1) sdram memory contro ller supports industry standard discrete devices that are compatible with both the ddr1 or ddr2 specifications. the correct i/o supply voltage must be provided for the two types of ddr devices: ddr1 devices re quire +2.5v and ddr2 devices require +1.8v. global memory timings, address and bank sizes, and memory addressing modes are programmable. features include: ? 32-bit memory interface for ddr1 ? 32- or 64-bit memory interface for ddr2 ? optional error checking and correcting (ecc) ? 2.6-gb/s peak data rate ? two memory banks of up to 1 gb each ? maximum capacity of 2gb ? support for 256-mb, 512-mb, and 1-gb ddr devices, with cas latencies of 2 or 3 ? support for ddr266/3 33 and ddr2-266/333. (faster parts may be used but must be clocked no faster than 166mhz) ? page mode accesses (up to 16 open pages) with configurable paging policy ? programmable address mapping and timing ? software initia ted self-refresh ? power management (self-refresh, suspend, sleep) ? one or two chip selects external peripheral bus controller (ebc) features include: ? up to six rom, eprom, sram, flash memory , and slave peripheral i/o banks supported ? up to 83mhz operation ? burst and non-burst devices ? 32-bit byte-addressable data bus ?data parity ? 30-bit address ? peripheral device pacing with external ?ready? ? latch data on ready, synchronous or asynchronous ? programmable access timing per device ? 256 wait states for non-burst ? 32 burst wait states for first access and up to 8 wait states for subsequent accesses ? programmable cson, csoff relative to address ? programmable oeon, weon, weoff (1 to 4 clock cycles) relative to cs ? programmable address mapping ? external dma slave support ? external master interface ? write posting from external master ? read prefetching on plb for external master reads ? bursting capable from external master ? allows external master access to all non-ebc plb slaves ? external master can control ebc slaves for access 440GRX ? ppc440GRX embedded processor preliminary data sheet 14 amcc proprietary revision 1.08 ? october 15, 2007 ethernet controller ethernet support provided by the ppc440GRX interfaces to the physical layer but the phy is not included on the chip: ? two 10/100/1000 interfaces running in full- and half-duplex modes providing: ? one gigabit media independent interface (gmii) ? one media independent interface (mii) ? two reduced gigabit mii (rgmii) ? two serial mii (smii) at 100/10mbps. ? packet reject support ? jumbo frame support ? dma capability ? interrupt coalescence dma-to-plb3 (64-bit) controller this dma controller provides a dma interface between opb0 and plb3. features include: ? supports the following transfers: ? memory-to-memory transfers ? buffered peripheral to memory transfers ? buffered memory to peripheral transfers ? four channels ? scatter/gather capability for pr ogramming multiple dma operations ? 32-byte buffer ? 8-, 16-, 32-bit peripheral support (opb and external) ? 32-bit addressing ? address increment or decrement ? supports internal and external peripherals ? support for memory mapped peripherals ? support for peripherals running on slower frequency buses serial ports (uart) features include: ? up to four ports in th e following combinations: ? one 8-pin (uart0) ? two 4-pin (uart0 and uart1) ? one 4-pin (uart0) and two 2-pin (uart1 and uart2) ? four 2-pin (uart0, uart1, uart2, and uart3) ? selectable internal or external serial clock to allow wide range of baud rates ? register compatibility wit h ns16750 register set ? complete status reporting capability ? fully programmable serial-i nterface characteristics ? supports dma using internal dma function on plb3 440GRX ? ppc440GRX embedded processor revision 1.08 ? october 15, 2007 amcc proprietary 15 preliminary data sheet iic bus controller features include: ? two iic interfaces provided ? support for philips? semiconductors i 2 c specification, dated 1995 ? operation at 100khz or 400khz ?8-bit data ? 10- or 7-bit address ? slave transmitter and receiver ? master transmitter and receiver ? multiple bus masters ? two independent 4 x 1 byte data buffers ? twelve memory-mapped, fully prog rammable configur ation registers ? one programmable interrupt request signal ? provides full management of all iic bus protocols ? programmable error recovery ? includes an integrated bootstrap controller (bsc) that is multiplexed with the second iic interface serial peripheral co ntroller (spi/scp) the serial peripheral interface (also known as the se rial communications port) is a full-duplex, synchronous, character-oriented (byte) port that allo ws the exchange of data with other serial devices. the scp is a master on the serial port supporting a 3-wire in terface (receive, transmit, and clock), and is a slave on the opb. features include: ? three-wire serial port interface ? full-duplex synchronous operation ? scp bus master ? opb bus slave ? programmable clock rate divider ? clock inversion ? reverse data ? local data loop back for test nand flash controller the nand flash controller provides a simple interface bet ween the ebc and up to four separate external nand flash devices. it provides both direct command, address, and data access to the external device as well as a memory-mapped linear region that gener ates data accesses. nand flash data is transferred on the peripheral data bus. features include: ? one to four banks supported on ebc ? direct interface to: ? discrete nand flash devices (up to four devices) ? smartmedia card socket (22-pins) ? device sizes: ? 4mb and larger supported for read/write access ? 4mb to 256mb for boot-from-nand flash (size supported depends on addressing mode) ? (512 + 16)-b or (2k + 64)-b page sizes supported ?boot-from-nand ? execute up to 4kb of boot code out of first block. ? automatic page read accesses performed bas ed on device configuration and addressing mode. ? ecc provides single-bit error correction and double-bit error detection in each 256b of stored data 440GRX ? ppc440GRX embedded processor preliminary data sheet 16 amcc proprietary revision 1.08 ? october 15, 2007 general purpose timers (gpt) provides a separate time base counter and additional system timers in addition to those defined in the processor. features include: ? 32-bit time base counter dr iven by the opb bus clock ? seven 32-bit compare timers general purpose io (gpio) controller ? controller functions and gpio registers are programm ed and accessed via memory-mapped opb bus master accesses. ? 64 gpios are multiplexed with other functions. dcrs control whether a particular pin that has gpio capabilities acts as a gpio or is used for ano ther purpose. ? each gpio output is separately programmable to emulate an open drain driver (that is, drives to zero, tri-stated if output bit is 1). universal interrupt controller (uic) two universal interrupt controllers (uic) are employed. they provide control, status, and communications necessary between the external and internal source s of interrupts and the on-chip powerpc processor. note: processor specific interrupts (for exampl e, page faults) do not use uic resources. features include: ? 10 external interrupts ? edge triggered or level-sensitive ? positive or negative active ? non-critical or critical interrupt to the on-chip processor ? programmable interrupt priority ordering ? programmable critical interrupt ve ctor for faster vector processing jtag features include: ? ieee 1149.1 test access port ? jtag boundary scan description language (bsdl) ? refer to http://www.amcc.com/ embedded/partners for a list of amcc partners supplying probes for use with this port. 440GRX ? ppc440GRX embedded processor revision 1.08 ? october 15, 2007 amcc proprietary 17 preliminary data sheet package diagram figure 3. 35mm, 680-ball te-pbga package 35.0 35.0 gold gate release corresponds to pcb substrate mold compound a1 ball location top view bottom view notes: 1. all dimensions are in mm. 2. package is available with le ad or lead-free (rohs compliant). 30.0 typ 24.0 typ a 26 af b c d e f g h j k l m aa n p r t u v w y ab ac ad ae thermal balls 135 7 911131517 19 2 4 6 810 12 14 16 18 21 23 25 20 22 24 34 27 29 31 33 28 30 32 ap aj ag ah ak al am an 33.0 1.0 680 x 0.60 0.10 solder ball 9.0 2.65 max 0.3 - 0.6 3. package conforms to jedec ms-034. ppc440GRX e1 1ywwbzzzzz ppc440GRX-nprffft ? ccccccc part number lot number (zzzzz) 440GRX ? ppc440GRX embedded processor preliminary data sheet 18 amcc proprietary revision 1.08 ? october 15, 2007 assembly recommendations table 3. recommended reflow soldering profile profile feature sn-pb eutectic assembly pb free reflow assembly average ramp-up rate 3 c/second max 3 c/second max preheat ? temperature min ? temperature max ? time (min to max) 100 c 150 c 60-120 seconds 150 c 180 c 60-120 seconds time maintained above: ? temperature ?time 183 c 60-150 seconds 230 c 30-50 seconds peak temperature 225 +0/-5 c 260 +5/-0 c time within 5 c of actual peak temperature 10-30 seconds 10-20 seconds ramp-down rate 6 c/second max 6 c/second max time 25 c to peak temperature 6 minutes max 8 minutes max table 4. jedec moisture sensit ivity level and ball composition sn-pb eutectic assembly pb free reflow assembly msl level 3 3 solder ball metallurgy 63sn/37pb sn/4ag/05cu 440GRX ? ppc440GRX embedded processor revision 1.08 ? october 15, 2007 amcc proprietary 19 preliminary data sheet signal lists the following table lists all the external signals in alphab etical order and shows the ball (pin) number on which the signal appears. multiplexed signals are shown with the default signal (following reset) not in brackets and alternate signals in brackets. multiplexed signals appear alphabetically multiple times in the list? once for each signal name on the ball. the page number listed gives the page in table 9 on page 56 where the signals in the indicated interface group begin. in cases where signals in the same interface group (for exampl e, ethernet) have different names to distinguish variations in the mode of operation, the names are separated by a comma with the primary mode name appearing first. in cases where the signals ha ve the same function but are associated with different ports (for example, uart), the signals are separated by a slash (/). these signals are listed only once, and appear alphabetically by the primary mode or primary port name. alphabetical signal list table 5. signals listed alphabetically (sheet 1 of 26) signal name ball interface group page agnd ap25 power 63 av dd ap24 ba0 aj03 ddr sdram 57 ba1 ak03 ba2 ap08 banksel0 ah02 ddr sdram 57 banksel1 ah01 [busreq]gpio31 p04 external master peripheral 60 cas ah04 ddr sdram 57 clken an09 ddr sdram 57 dm0 al21 ddr sdram 57 dm1 am18 dm2 ap15 dm3 al14 dm4 ae04 dm5 ab03 dm6 y01 dm7 u03 dm8 an10 [dmaack0][irq8]gpio47 t34 external slave peripheral 59 [dmaack1][irq4]gpio44 v32 [dmaack2][peraddr06]gpio01 c25 [dmaack3][peraddr03]gpio04 d26 [dmareq0][irq7]gpio46 u32 external slave peripheral 59 [dmareq1]irq5[modectrl] w34 [dmareq2][peraddr07]gpio00 b25 [dmareq3][peraddr04]gpio03 a26 440GRX ? ppc440GRX embedded processor preliminary data sheet 20 amcc proprietary revision 1.08 ? october 15, 2007 dqs0 am21 ddr sdram 57 dqs1 am19 dqs2 al16 dqs3 am13 dqs4 ae03 dqs5 ab04 dqs6 w04 dqs7 u04 dqs8 ap10 drvrinh1 r02 system 62 [drvrinh2]halt e32 eagnd ap27 power 63 eav dd ap28 ecc0 am11 ddr sdram 57 ecc1 al11 ecc2 am09 ecc3 al09 ecc4 ap11 ecc5 an11 ecc6 am10 ecc7 ap09 [eot0/tc0][irq9]gpio48 t32 external slave peripheral 59 [eot1/tc1][irq6]gpio45 u33 [eot2/tc2][peraddr05]gpio02 d25 [eot3/tc3][peraddr02]gpio05 c26 eov dd aa22 power 63 eov dd ab21 eov dd ac33 eov dd af30 eov dd ah30 eov dd aj30 eov dd ak26 eov dd ak28 eov dd ak29 eov dd ak33 eov dd an23 eov dd an30 [extack ]gpio30 m03 external master peripheral 60 table 5. signals listed alphabetically (sheet 2 of 26) signal name ball interface group page 440GRX ? ppc440GRX embedded processor revision 1.08 ? october 15, 2007 amcc proprietary 21 preliminary data sheet [extreq ]gpio27 a04 external master peripheral 60 extreset d06 external master peripheral 60 gmccd, gmc1rxclk aj32 ethernet 58 gmccrs, gmc1txclk ak32 gmcgtxclk, gmc0txclk am27 gmcmdclk al34 gmcmdio ak34 gmcrefclk, smiirefclk aj33 gmcrxclk, gmc0rxclk smiisync an28 gmcrxd0, gmc0rxd0, tbirxd0, rtbi0rxd0, smii0rxd al28 gmcrxd1, gmc0rxd1 smii1rxd ap29 gmcrxd2, gmc0rxd2 am28 gmcrxd3, gmc0rxd3 an29 gmcrxd4, gmc1rxd0 am29 gmcrxd5, gmc1rxd1 ap30 gmcrxd6, gmc1rxd22 ap31 gmcrxd7, gmc1rxd3 am30 gmcrxdv, gmc0rxctl aj31 gmcrxer, gmc1rxctl al33 gmctxclk al27 gmctxd0, gmc0txd0 smii0txd al24 gmctxd1, gmc0txd, smii1txd an25 [gmctxd2, gmc0txd2] gpio24 am25 [gmctxd3, gmc0txd3] gpio25 al25 [gmctxd4, gmc1txd0] gpio16 ap26 [gmctxd5, gmc1txd1] gpio17 al26 [gmctxd6, gmc1txd2] gpio18 an26 [gmctxd7, gmc1txd3] gpio19 am26 gmctxer, gmc1txctl am24 gmctxen, gmc0txctl an24 table 5. signals listed alphabetically (sheet 3 of 26) signal name ball interface group page 440GRX ? ppc440GRX embedded processor preliminary data sheet 22 amcc proprietary revision 1.08 ? october 15, 2007 gnd a01 power 63 gnd a02 gnd a03 gnd a28 gnd a32 gnd a33 gnd a34 gnd b01 gnd b02 gnd b03 gnd b04 gnd b08 gnd b16 gnd b19 gnd b26 gnd b27 gnd b31 gnd b32 gnd b33 gnd b34 gnd c02 gnd c03 gnd c04 gnd c31 gnd c32 gnd c33 gnd c34 gnd d03 gnd d04 gnd d05 gnd d30 gnd d31 gnd d32 gnd d33 gnd e05 gnd e08 gnd e10 table 5. signals listed alphabetically (sheet 4 of 26) signal name ball interface group page 440GRX ? ppc440GRX embedded processor revision 1.08 ? october 15, 2007 amcc proprietary 23 preliminary data sheet gnd e16 power 63 gnd e18 gnd e19 gnd e25 gnd e27 gnd e30 gnd e31 gnd h01 gnd h02 gnd h05 gnd h30 gnd h33 gnd k01 gnd k04 gnd k05 gnd k30 gnd j03 gnd m01 gnd m04 gnd n01 gnd n04 gnd n13 gnd n15 gnd n17 gnd n18 gnd n20 gnd n22 gnd p14 gnd p15 gnd p17 gnd p18 gnd p20 gnd p21 gnd r13 gnd r14 gnd r15 gnd r16 table 5. signals listed alphabetically (sheet 5 of 26) signal name ball interface group page 440GRX ? ppc440GRX embedded processor preliminary data sheet 24 amcc proprietary revision 1.08 ? october 15, 2007 gnd r17 power 63 gnd r18 gnd r19 gnd r20 gnd r21 gnd r22 gnd t02 gnd t05 gnd t15 gnd t16 gnd t17 gnd t18 gnd t19 gnd t20 gnd t30 gnd t33 gnd u05 gnd u13 gnd u14 gnd u15 gnd u16 gnd u17 gnd u18 gnd u19 gnd u20 gnd u21 gnd u22 gnd v13 gnd v14 gnd v15 gnd v16 gnd v17 gnd v18 gnd v19 gnd v20 gnd v21 gnd v22 table 5. signals listed alphabetically (sheet 6 of 26) signal name ball interface group page 440GRX ? ppc440GRX embedded processor revision 1.08 ? october 15, 2007 amcc proprietary 25 preliminary data sheet gnd v30 power 63 gnd w02 gnd w05 gnd w15 gnd w16 gnd w17 gnd w18 gnd w19 gnd w20 gnd w30 gnd w33 gnd y13 gnd y14 gnd y15 gnd y16 gnd y17 gnd y18 gnd y19 gnd y20 gnd y21 gnd y22 gnd aa14 gnd aa15 gnd aa17 gnd aa18 gnd aa20 gnd aa21 gnd ab13 gnd ab15 gnd ab17 gnd ab18 gnd ab20 gnd ab22 gnd ad01 gnd ae05 gnd ae30 gnd ag02 table 5. signals listed alphabetically (sheet 7 of 26) signal name ball interface group page 440GRX ? ppc440GRX embedded processor preliminary data sheet 26 amcc proprietary revision 1.08 ? october 15, 2007 gnd ag05 power 63 gnd ag30 gnd ag33 gnd aj01 gnd ak04 gnd ak05 gnd ak08 gnd ak10 gnd ak16 gnd ak17 gnd ak19 gnd ak25 gnd ak27 gnd ak30 gnd ak31 gnd al03 gnd al04 gnd al05 gnd al06 gnd al29 gnd al30 gnd al31 gnd al32 gnd am01 gnd am02 gnd am03 gnd am04 gnd am31 gnd am32 gnd am33 gnd am34 gnd an01 gnd an02 gnd an03 gnd an04 gnd an08 gnd an16 table 5. signals listed alphabetically (sheet 8 of 26) signal name ball interface group page 440GRX ? ppc440GRX embedded processor revision 1.08 ? october 15, 2007 amcc proprietary 27 preliminary data sheet gnd an19 power 63 gnd an27 gnd an31 gnd an32 gnd an33 gnd an34 gnd ap01 gnd ap02 gnd ap03 gnd ap32 gnd ap33 gnd ap34 table 5. signals listed alphabetically (sheet 9 of 26) signal name ball interface group page 440GRX ? ppc440GRX embedded processor preliminary data sheet 28 amcc proprietary revision 1.08 ? october 15, 2007 gpio00[peraddr07][dmareq2] b25 system 62 gpio01[peraddr06][dmaack2] c25 gpio02[peraddr05][eot2/tc2] d25 gpio03[peraddr04][dmareq3] a26 gpio04[peraddr03][dmaack3] d26 gpio05[peraddr02][eot3/tc3] c26 gpio06[percs1 ][nfce1 ]b09 gpio07[percs2 ][nfce2 ]d09 gpio08[percs3 ][nfce3 ]d08 gpio09[percs4 ]a09 gpio10[percs5 ]a08 gpio11[pererr] c07 gpio12[nfren ]d17 gpio13[nfwen ]a16 gpio14[nfcle] a18 gpio15[nfale] b17 gpio16[gmctxd4, gmc1txd0] ap26 gpio17[gmctxd5, gmc1txd1] al26 gpio18[gmctxd6, gmc1txd2] an26 gpio19[gmctxd7, gmc1txd3] am26 gpio20[rejectpkt0] am23 gpio21[rejectpkt1] al23 gpio22[nfrdybusy ]a17 gpio23[scpdo] ab31 gpio24[gmctxd2, gmc0txd2] am25 gpio25[gmctxd3, gmc0txd3] al25 [gpio26]iic0sdata ab33 gpio27[usb2rxerr][extreq ]a04 gpio28[usb2txval] c06 gpio29[usb2susp][holdack] c05 gpio30[usb2xcvrsel][extack ]m03 gpio31[usb2termsel][busreq] p04 table 5. signals listed alphab etically (sheet 10 of 26) signal name ball interface group page 440GRX ? ppc440GRX embedded processor revision 1.08 ? october 15, 2007 amcc proprietary 29 preliminary data sheet gpio32[usb2om0][perdatapar2] r03 system 62 gpio33[usb2om1][perdatapar3] r04 gpio34[uart0_dcd /uart1_cts /uart2_tx] c28 gpio35[uart0_dsr /uart1_rts /uart2_rx] c29 gpio36[uart0_cts /uart3_rx][perdatapar0] a29 gpio37[uart0_rts /uart3_tx][perdatapar1] b29 gpio38[uart0_dtr /uart1_tx] d28 gpio39[uart0_ri /uart1_rx] b28 gpio40[irq0] ad33 gpio41[irq1] ac31 gpio42[irq2] ad34 gpio43[irq3] u34 gpio44[irq4][dmaack1] v32 gpio45[irq6][eot1/tc1] u33 gpio46[irq7][dmareq0] u32 gpio47[irq8[dmaack0] t34 gpio48[irq9][eot0/tc0] t32 gpio49[trcbs0] ae34 gpio50[trcbs1] ae32 gpio51[trcbs2] ae33 gpio52[trces0] ae31 gpio53[trces1] af34 gpio54[trces2] af33 gpio55[trces3] af32 gpio56[trces4] af31 gpio57[trcts0] ag34 gpio58[trcts1] ag31 gpio59[trcts2] ah33 gpio60[trcts3] ah34 gpio61[trcts4] ah32 gpio62[trcts5] aj34 gpio63[trcts6] ah31 halt [drvrinh2] e32 system 62 [holdack]gpio29 c05 external master peripheral 60 holdpri[leaktest] p01 holdreq[rcvrinh] d07 iic0sclk ab32 iic0 peripheral 60 iic0sdata[gpio26] ab33 table 5. signals listed alph abetically (sheet 11 of 26) signal name ball interface group page 440GRX ? ppc440GRX embedded processor preliminary data sheet 30 amcc proprietary revision 1.08 ? october 15, 2007 [iic1sclk]scpclkout ac34 iic1 peripheral 60 [iic1sdata]scpdi ac32 [irq0]gpio40 ad33 interrupts 61 [irq1]gpio41 ac31 [irq2]gpio42 ad34 [irq3]gpio43 u34 [irq4]gpio44[dmaack1] v32 irq5[modectrl][dmareq1] w34 [irq6]gpio45[eot1/tc1] u33 [irq7]gpio46[dmareq0] u32 [irq8]gpio47[dmaack0] t34 [irq9]gpio48[eot0/tc0] t32 [leaktest]holdpri p01 system 62 leaktest2 c08 memaddr00 am05 ddr sdram 57 memaddr01 ap04 memaddr02 ap05 memaddr03 am06 memaddr04 ap06 memaddr05 an06 memaddr06 al07 memaddr07 an07 memaddr08 am07 memaddr09 ap07 memaddr10 al02 memaddr11 al08 memaddr12 am08 memaddr13 ag04 memclkout al01 ddr sdram 57 memclkout ak01 table 5. signals listed alphab etically (sheet 12 of 26) signal name ball interface group page 440GRX ? ppc440GRX embedded processor revision 1.08 ? october 15, 2007 amcc proprietary 31 preliminary data sheet memdata00 an22 ddr sdram 57 memdata01 ap22 memdata02 am20 memdata03 al20 memdata04 al22 memdata05 am22 memdata06 an21 memdata07 ap21 memdata08 ap20 memdata09 al18 memdata10 an17 memdata11 ap17 memdata12 an20 memdata13 ap19 memdata14 an18 memdata15 ap18 memdata16 am16 memdata17 ap16 memdata18 al15 memdata19 ap14 memdata20 al17 memdata21 am17 memdata22 an15 memdata23 am15 memdata24 ap13 memdata25 an13 memdata26 ap12 memdata27 al12 memdata28 am14 memdata29 an14 memdata30 al13 memdata31 am12 table 5. signals listed alphab etically (sheet 13 of 26) signal name ball interface group page 440GRX ? ppc440GRX embedded processor preliminary data sheet 32 amcc proprietary revision 1.08 ? october 15, 2007 memdata32 af03 ddr sdram 57 memdata33 af01 memdata34 ad04 memdata35 ad03 memdata36 ag03 memdata37 af02 memdata38 ae02 memdata39 ae01 memdata40 ac03 memdata41 ac01 memdata42 aa04 memdata43 aa03 memdata44 ad02 memdata45 ac04 memdata46 ab01 memdata47 ab02 memdata48 y03 memdata49 y02 memdata50 v04 memdata51 v03 memdata52 aa02 memdata53 aa01 memdata54 w03 memdata55 w01 memdata56 u01 memdata57 u02 memdata58 t04 memdata59 r01 memdata60 v02 memdata61 v01 memdata62 t01 memdata63 t03 memodt0 ah03 ddr sdram 57 memodt1 ag01 [modectrl]irq5[dmareq1] w34 system 62 table 5. signals listed alphab etically (sheet 14 of 26) signal name ball interface group page 440GRX ? ppc440GRX embedded processor revision 1.08 ? october 15, 2007 amcc proprietary 33 preliminary data sheet [nfale]gpio15 b17 nand flash 61 [nfce0 ]percs0 d10 [nfce1 ][percs1 ]gpio06 b09 [nfce2 ][percs2 ]gpio07 d09 [nfce3 ][percs3 ]gpio08 d08 [nfcle]gpio14 a18 [nfrdybusy ]gpio22 a17 [nfren ]gpio12 d17 [nfwen ]gpio13 a16 table 5. signals listed alphab etically (sheet 15 of 26) signal name ball interface group page 440GRX ? ppc440GRX embedded processor preliminary data sheet 34 amcc proprietary revision 1.08 ? october 15, 2007 no ball f06?f29 a physical ball does not exist at these ball coordinates. na no ball g06?g29 no ball h06?h29 no ball j06?j29 no ball k06?k29 no ball l06?l29 no ball m06?m29 no ball n06?n12 no ball n23?n29 no ball p06?p12 no ball p23?p29 no ball r06?r12 no ball r23?r29 no ball t06?t12 no ball t23?t29 no ball u06?u12 no ball u23?u29 no ball v06?v12 no ball v23?v29 no ball w06?w12 no ball w23?w29 no ball y06?y12 no ball y23?y29 no ball aa06?aa12 no ball aa23?aa29 no ball ab06?ab12 no ball ab23?ab29 no ball ac06?ac29 no ball ad06?ad29 no ball ae06?ae29 no ball af06?af29 no ball ag06?ag29 no ball ah06?ah29 no ball aj06?aj29 table 5. signals listed alphab etically (sheet 16 of 26) signal name ball interface group page 440GRX ? ppc440GRX embedded processor revision 1.08 ? october 15, 2007 amcc proprietary 35 preliminary data sheet ov dd b05 power 63 ov dd b12 ov dd b23 ov dd b30 ov dd e02 ov dd e06 ov dd e07 ov dd e09 ov dd e17 ov dd e26 ov dd e28 ov dd e29 ov dd e33 ov dd f05 ov dd f30 ov dd g05 ov dd g30 ov dd j04 ov dd j05 ov dd j30 ov dd l01 ov dd l02 ov dd l04 ov dd m02 ov dd m33 ov dd n14 ov dd n21 ov dd p13 ov dd p22 ov dd u30 table 5. signals listed alphab etically (sheet 17 of 26) signal name ball interface group page 440GRX ? ppc440GRX embedded processor preliminary data sheet 36 amcc proprietary revision 1.08 ? october 15, 2007 pciad00 d29 pci 56 pciad01 a30 pciad02 c30 pciad03 a31 pciad04 d34 pciad05 f31 pciad06 e34 pciad07 f32 pciad08 f33 pciad09 f34 pciad10 g31 pciad11 g33 pciad12 g34 pciad13 h31 pciad14 h32 pciad15 h34 pciad16 l31 pciad17 l33 pciad18 m32 pciad19 m31 pciad20 m34 pciad21 n31 pciad22 n33 pciad23 n32 pciad24 p31 pciad25 p33 pciad26 p32 pciad27 p34 pciad28 r31 pciad29 r32 pciad30 r33 pciad31 r34 pcic0/be0 g32 pci 56 pcic1/be1 j31 pcic2/be2 l34 pcic3/be3 n34 pciclk aa32 pci 56 pcidevsel k32 pci 56 pciframe l32 pci 56 table 5. signals listed alphab etically (sheet 18 of 26) signal name ball interface group page 440GRX ? ppc440GRX embedded processor revision 1.08 ? october 15, 2007 amcc proprietary 37 preliminary data sheet pcignt0 /req y34 pci 56 pcignt1 y33 pcignt2 y32 pcignt3 y31 pcignt4 aa33 pcignt5 aa34 pciidsel t31 pci 56 pciint ab34 pci 56 pciirdy k33 pci 56 pcipar j32 pci 56 pciperr j33 pci 56 pcireq0 /gnt v34 pci 56 pcireq1 u31 pcireq2 v33 pcireq3 v31 pcireq4 w32 pcireq5 w31 pcireset aa31 pci 56 pciserr j34 pci 56 pcistop k31 pci 56 pcitrdy k34 pci 56 table 5. signals listed alphab etically (sheet 19 of 26) signal name ball interface group page 440GRX ? ppc440GRX embedded processor preliminary data sheet 38 amcc proprietary revision 1.08 ? october 15, 2007 [peraddr02]gpio05[eot3/tc3] c26 external slave peripheral 59 [peraddr03]gpio04[dmaack3] d26 [peraddr04]gpio03[dmareq3] a26 [peraddr05]gpio02[eot2/tc2] d25 [peraddr06]gpio01[dmaack2] c25 [peraddr07]gpio00[dmareq2] b25 peraddr08 a25 peraddr09 c24 peraddr10 d24 peraddr11 b24 peraddr12 d23 peraddr13 a24 peraddr14 c23 peraddr15 a23 peraddr16 d22 peraddr17 c22 peraddr18 a22 peraddr19 d21 peraddr20 c21 peraddr21 b21 peraddr22 a21 peraddr23 d20 peraddr24 c20 peraddr25 b20 peraddr26 d19 peraddr27 c19 peraddr28 a19 peraddr29 d18 peraddr30 c18 peraddr31 b18 perblast b07 external slave peripheral 59 perclk a07 external master peripheral 60 percs0 [nfce0 ]d10 external slave peripheral 59 [percs1 ][nfce1 ]gpio06 b09 [percs2 ][nfce2 ]gpio07 d09 [percs3 ][nfce3 ]gpio08 d08 [percs4 ]gpio09 a09 [percs5 ]gpio10 a08 table 5. signals listed alphab etically (sheet 20 of 26) signal name ball interface group page 440GRX ? ppc440GRX embedded processor revision 1.08 ? october 15, 2007 amcc proprietary 39 preliminary data sheet perdata00 c14 external slave peripheral 59 perdata01 d14 perdata02 a13 perdata03 b13 perdata04 c13 perdata05 d13 perdata06 a12 perdata07 c12 perdata08 a11 perdata09 d12 perdata10 b11 perdata11 c11 perdata12 d11 perdata13 a10 perdata14 b10 perdata15 c10 perdata16 e03 perdata17 c01 perdata18 d02 perdata19 e04 perdata20 d01 perdata21 e01 perdata22 f04 perdata23 f03 perdata24 f02 perdata25 f01 perdata26 g03 perdata27 g04 perdata28 g02 perdata29 g01 perdata30 h04 perdata31 h03 [perdatapar0]gpio36[uart0_cts /uart3_rx] a29 [perdatapar1]gpio37[uart0_rts //uart3_tx] b29 [perdatapar2]gpio32 r03 [perdatapar3]gpio33 r04 [pererr]gpio11 c07 external master peripheral 59 peroe b14 external slave peripheral 59 perready c17 external slave peripheral 59 table 5. signals listed alphab etically (sheet 21 of 26) signal name ball interface group page 440GRX ? ppc440GRX embedded processor preliminary data sheet 40 amcc proprietary revision 1.08 ? october 15, 2007 perr/w a14 external slave peripheral 59 perwbe0 a15 external slave peripheral 59 perwbe1 b15 perwbe2 c15 perwbe3 d15 psroout a20 system 62 ras aj04 ddr sdram 57 [rcvrinh]holdreq d07 system 62 refen b06 system 62 [rejectpkt0]gpio20 am23 ethernet 58 [rejectpkt1]gpio21 al23 reserved a05 reserved 63 reserved j01 reserved j02 reserved l03 reserved n02 reserved n03 scpclkout[iic1sclk] ac34 serial peripheral (spi) 61 scpdi[iic1sdata] ac32 [scpdo]gpio23 ab31 sov dd v05 power 63 sov dd aa13 sov dd ab14 sov dd ac02 sov dd af05 sov dd ah05 sov dd aj05 sov dd ak02 sov dd ak06 sov dd ak07 sov dd ak09 sov dd ak18 sov dd an05 sov dd an12 table 5. signals listed alphab etically (sheet 22 of 26) signal name ball interface group page 440GRX ? ppc440GRX embedded processor revision 1.08 ? october 15, 2007 amcc proprietary 41 preliminary data sheet sv ref1a y04 ddr sdram 57 sv ref1b al10 sv ref2a af04 sv ref2b al19 sysclk ap23 system 62 syserr ad32 system 62 sysreset ad31 system 62 tck p02 jtag 61 tdi k03 jtag 61 tdo b22 jtag 61 testen c09 system 62 thermona c16 system 62 thermonb d16 tmrclk p03 system 62 tms k02 jtag 61 [trcbs0]gpio49 ae34 trace 63 [trcbs1]gpio50 ae32 [trcbs2]gpio51 ae33 trcclk ag32 trace 63 [trces0]gpio52 ae31 trace 63 [trces1]gpio53 af34 [trces2]gpio54 af33 [trces3]gpio55 af32 [trces4]gpio56 af31 [trcts0]gpio57 ag34 trace 63 [trcts1]gpio58 ag31 [trcts2]gpio59 ah33 [trcts3]gpio60 ah34 [trcts4]gpio61 ah32 [trcts5]gpio62 aj34 [trcts6]gpio63 ah31 trst a06 jtag 61 table 5. signals listed alphab etically (sheet 23 of 26) signal name ball interface group page 440GRX ? ppc440GRX embedded processor preliminary data sheet 42 amcc proprietary revision 1.08 ? october 15, 2007 [uart0_cts /uart3_rx]gpio36[perdatapar0] a29 uart peripheral 60 [uart0_dcd /uart1_cts /uart2_tx]gpio34 c28 [uart0_dsr /uart1_rts /uart2_rx]gpio35 c29 [uart0_dtr /uart1_tx]gpio38 d28 [uart0_ri /uart1_rx]gpio39 b28 [uart0_rts /uart3_tx]gpio37[perdatapar1] b29 uart0_rx c27 uartserclk a27 uart0_tx d27 table 5. signals listed alphab etically (sheet 24 of 26) signal name ball interface group page 440GRX ? ppc440GRX embedded processor revision 1.08 ? october 15, 2007 amcc proprietary 43 preliminary data sheet v dd e11 power 63 v dd e12 v dd e13 v dd e14 v dd e15 v dd e20 v dd e21 v dd e22 v dd e23 v dd e24 v dd l05 v dd l30 v dd m05 v dd m30 v dd n05 v dd n16 v dd n19 v dd n30 v dd p05 v dd p16 v dd p19 v dd p30 v dd r05 v dd r30 v dd t13 v dd t14 v dd t21 v dd t22 v dd w13 v dd w14 v dd w21 v dd w22 v dd y05 v dd y30 table 5. signals listed alphab etically (sheet 25 of 26) signal name ball interface group page 440GRX ? ppc440GRX embedded processor preliminary data sheet 44 amcc proprietary revision 1.08 ? october 15, 2007 signals in ball assignment order in the following table, only the primary (default) signal name is shown for each ball. multiplexed or multifunction signals are marked with an asterisk (*). to determine what other signals or fu nctions are on those balls, look up the primary signal name in table 5 on page 19. v dd aa05 power 63 v dd aa16 v dd aa19 v dd aa30 v dd ab05 v dd ab16 v dd ab19 v dd ab30 v dd ac05 v dd ac30 v dd ad05 v dd ad30 v dd ak11 v dd ak12 v dd ak13 v dd ak14 v dd ak15 v dd ak20 v dd ak21 v dd ak22 v dd ak23 v dd ak24 we aj02 ddr sdram 57 table 5. signals listed alphab etically (sheet 26 of 26) signal name ball interface group page 440GRX ? ppc440GRX embedded processor revision 1.08 ? october 15, 2007 amcc proprietary 45 preliminary data sheet table 6. signals listed by ba ll assignment (sheet 1 of 9) ball signal name ball signal name ball signal name ball signal name a01 gnd b01 gnd c01 perdata17 d01 perdata20 a02 gnd b02 gnd c02 gnd d02 perdata18 a03 gnd b03 gnd c03 gnd d03 gnd a04 gpio27* b04 gnd c04 gnd d04 gnd a05 reserved b05 ov dd c05gpio29* d05gnd a06 trst b06 refen c06 gpio28* d06 extreset a07 perclk b07 perblast c07 gpio11* d07 holdreq* a08 gpio10* b08 gnd c08 leaktest2 d08 gpio08* a09 gpio09* b09 gpio06* c09 testen d09 gpio07* a10 perdata13 b10 perdata14 c10 perdata15 d10 percs0 * a11 perdata08 b11 perdata10 c11 perdata11 d11 perdata12 a12 perdata06 b12 ov dd c12 perdata07 d12 perdata09 a13 perdata02 b13 perdata03 c13 perdata04 d13 perdata05 a14 perr/w b14 peroe c14 perdata00 d14 perdata01 a15 perwbe0 b15 perwbe1 c15 perwbe2 d15 perwbe3 a16 gpio13* b16 gnd c16 thermona d16 thermonb a17 gpio22* b17 gpio15* c17 perready d17 gpio12* a18 gpio14* b18 peraddr31 c18 peraddr30 d18 peraddr29 a19 peraddr28 b19 gnd c19 peraddr27 d19 peraddr26 a20 psroout b20 peraddr25 c20 peraddr24 d20 peraddr23 a21 peraddr22 b21 peraddr21 c21 peraddr20 d21 peraddr19 a22 peraddr18 b22 tdo c22 peraddr17 d22 peraddr16 a23 peraddr15 b23 ov dd c23 peraddr14 d23 peraddr12 a24 peraddr13 b24 peraddr11 c24 peraddr09 d24 peraddr10 a25 peraddr08 b25 gpio00* c25 gpio01* d25 gpio02* a26 gpio03* b26 gnd c26 gpio05* d26 gpio04* a27 uartserclk b27 gnd c27 uart0_rx* d27 uart0_tx* a28 gnd b28 gpio39* c28 gpio34* d28 gpio38* a29 gpio36* b29 gpio37* c29 gpio35* d29 pciad00 a30 pciad01 b30 ov dd c30 pciad02 d30 gnd a31 pciad03 b31 gnd c31 gnd d31 gnd a32 gnd b32 gnd c32 gnd d32 gnd a33 gnd b33 gnd c33 gnd d33 gnd a34 gnd b34 gnd c34 gnd d34 pciad04 440GRX ? ppc440GRX embedded processor preliminary data sheet 46 amcc proprietary revision 1.08 ? october 15, 2007 e01 perdata21 f01 perdata25 g01 perdata29 h01 gnd e02 ov dd f02 perdata24 g02 perdata28 h02 gnd e03 perdata16 f03 perdata23 g03 perdata26 h03 perdata31 e04 perdata19 f04 perdata22 g04 perdata27 h04 perdata30 e05 gnd f05 ov dd g05 ov dd h05 gnd e06 ov dd f06 no ball g06 no ball h06 no ball e07 ov dd f07 no ball g07 no ball h07 no ball e08 gnd f08 no ball g08 no ball h08 no ball e09 ov dd f09 no ball g09 no ball h09 no ball e10 gnd f10 no ball g10 no ball h10 no ball e11 v dd f11 no ball g11 no ball h11 no ball e12 v dd f12 no ball g12 no ball h12 no ball e13 v dd f13 no ball g13 no ball h13 no ball e14 v dd f14 no ball g14 no ball h14 no ball e15 v dd f15 no ball g15 no ball h15 no ball e16 gnd f16 no ball g16 no ball h16 no ball e17 ov dd f17 no ball g17 no ball h17 no ball e18 gnd f18 no ball g18 no ball h18 no ball e19 gnd f19 no ball g19 no ball h19 no ball e20 v dd f20 no ball g20 no ball h20 no ball e21 v dd f21 no ball g21 no ball h21 no ball e22 v dd f22 no ball g22 no ball h22 no ball e23 v dd f23 no ball g23 no ball h23 no ball e24 v dd f24 no ball g24 no ball h24 no ball e25 gnd f25 no ball g25 no ball h25 no ball e26 ov dd f26 no ball g26 no ball h26 no ball e27 gnd f27 no ball g27 no ball h27 no ball e28 ov dd f28 no ball g28 no ball h28 no ball e29 ov dd f29 no ball g29 no ball h29 no ball e30 gnd f30 ov dd g30 ov dd h30 gnd e31 gnd f31 pciad05 g31 pciad10 h31 pciad13 e32 halt * f32 pciad07 g32 pcic0/be0 h32 pciad14 e33 ov dd f33 pciad08 g33 pciad11 h33 gnd e34 pciad06 f34 pciad09 g34 pciad12 h34 pciad15 table 6. signals listed by ba ll assignment (sheet 2 of 9) ball signal name ball signal name ball signal name ball signal name 440GRX ? ppc440GRX embedded processor revision 1.08 ? october 15, 2007 amcc proprietary 47 preliminary data sheet j01 reserved k01 gnd l01 ov dd m01 gnd j02 reserved k02 tms l02 ov dd m02 ov dd j03 gnd k03 tdi l03 reserved m03 gpio30* j04 ov dd k04 gnd l04 ov dd m04 gnd j05 ov dd k05 gnd l05 v dd m05 v dd j06 no ball k06 no ball l06 no ball m06 no ball j07 no ball k07 no ball l07 no ball m07 no ball j08 no ball k08 no ball l08 no ball m08 no ball j09 no ball k09 no ball l09 no ball m09 no ball j10 no ball k10 no ball l10 no ball m10 no ball j11 no ball k11 no ball l11 no ball m11 no ball j12 no ball k12 no ball l12 no ball m12 no ball j13 no ball k13 no ball l13 no ball m13 no ball j14 no ball k14 no ball l14 no ball m14 no ball j15 no ball k15 no ball l15 no ball m15 no ball j16 no ball k16 no ball l16 no ball m16 no ball j17 no ball k17 no ball l17 no ball m17 no ball j18 no ball k18 no ball l18 no ball m18 no ball j19 no ball k19 no ball l19 no ball m19 no ball j20 no ball k20 no ball l20 no ball m20 no ball j21 no ball k21 no ball l21 no ball m21 no ball j22 no ball k22 no ball l22 no ball m22 no ball j23 no ball k23 no ball l23 no ball m23 no ball j24 no ball k24 no ball l24 no ball m24 no ball j25 no ball k25 no ball l25 no ball m25 no ball j26 no ball k26 no ball l26 no ball m26 no ball j27 no ball k27 no ball l27 no ball m27 no ball j28 no ball k28 no ball l28 no ball m28 no ball j29 no ball k29 no ball l29 no ball m29 no ball j30 ov dd k30 gnd l30 v dd m30 v dd j31 pcic1/be1 k31 pcistop l31 pciad16 m31 pciad19 j32 pcipar k32 pcidevsel l32 pciframe m32 pciad18 j33 pciperr k33 pciirdy l33 pciad17 m33 ov dd j34 pciserr k34 pcitrdy l34 pcic2/be2 m34 pciad20 table 6. signals listed by ba ll assignment (sheet 3 of 9) ball signal name ball signal name ball signal name ball signal name 440GRX ? ppc440GRX embedded processor preliminary data sheet 48 amcc proprietary revision 1.08 ? october 15, 2007 n01 gnd p01 holdpri* r01 memdata59 t01 memdata62 n02 reserved p02 tck r02 drvrinh1 t02 gnd n03 reserved p03 tmrclk r03 gpio32* t03 memdata63 n04 gnd p04 gpio31* r04 gpio33* t04 memdata58 n05 v dd p05 v dd r05 v dd t05 gnd n06 no ball p06 no ball r06 no ball t06 no ball n07 no ball p07 no ball r07 no ball t07 no ball n08 no ball p08 no ball r08 no ball t08 no ball n09 no ball p09 no ball r09 no ball t09 no ball n10 no ball p10 no ball r10 no ball t10 no ball n11 no ball p11 no ball r11 no ball t11 no ball n12 no ball p12 no ball r12 no ball t12 no ball n13 gnd p13 ov dd r13 gnd t13 v dd n14 ov dd p14 gnd r14 gnd t14 v dd n15 gnd p15 gnd r15 gnd t15 gnd n16 v dd p16 v dd r16 gnd t16 gnd n17 gnd p17 gnd r17 gnd t17 gnd n18 gnd p18 gnd r18 gnd t18 gnd n19 v dd p19 v dd r19 gnd t19 gnd n20 gnd p20 gnd r20 gnd t20 gnd n21 ov dd p21 gnd r21 gnd t21 v dd n22 gnd p22 ov dd r22 gnd t22 v dd n23 no ball p23 no ball r23 no ball t23 no ball n24 no ball p24 no ball r24 no ball t24 no ball n25 no ball p25 no ball r25 no ball t25 no ball n26 no ball p26 no ball r26 no ball t26 no ball n27 no ball p27 no ball r27 no ball t27 no ball n28 no ball p28 no ball r28 no ball t28 no ball n29 no ball p29 no ball r29 no ball t29 no ball n30 v dd p30 v dd r30 v dd t30 gnd n31 pciad21 p31 pciad24 r31 pciad28 t31 pciidsel n32 pciad23 p32 pciad26 r32 pciad29 t32 gpio48* n33 pciad22 p33 pciad25 r33 pciad30 t33 gnd n34 pcic3/be3 p34 pciad27 r34 pciad31 t34 gpio47* table 6. signals listed by ba ll assignment (sheet 4 of 9) ball signal name ball signal name ball signal name ball signal name 440GRX ? ppc440GRX embedded processor revision 1.08 ? october 15, 2007 amcc proprietary 49 preliminary data sheet u01 memdata56 v01 memdata61 w01 memdata55 y01 dm6 u02 memdata57 v02 memdata60 w02 gnd y02 memdata49 u03 dm7 v03 memdata51 w03 memdata54 y03 memdata48 u04 dqs7 v04 memdata50 w04 dqs6 y04 sv ref1a u05 gnd v05 sov dd w05 gnd y05 v dd u06 no ball v06 no ball w06 no ball y06 no ball u07 no ball v07 no ball w07 no ball y07 no ball u08 no ball v08 no ball w08 no ball y08 no ball u09 no ball v09 no ball w09 no ball y09 no ball u10 no ball v10 no ball w10 no ball y10 no ball u11 no ball v11 no ball w11 no ball y11 no ball u12 no ball v12 no ball w12 no ball y12 no ball u13 gnd v13 gnd w13 v dd y13 gnd u14 gnd v14 gnd w14 v dd y14 gnd u15 gnd v15 gnd w15 gnd y15 gnd u16 gnd v16 gnd w16 gnd y16 gnd u17 gnd v17 gnd w17 gnd y17 gnd u18 gnd v18 gnd w18 gnd y18 gnd u19 gnd v19 gnd w19 gnd y19 gnd u20 gnd v20 gnd w20 gnd y20 gnd u21 gnd v21 gnd w21 v dd y21 gnd u22 gnd v22 gnd w22 v dd y22 gnd u23 no ball v23 no ball w23 no ball y23 no ball u24 no ball v24 no ball w24 no ball y24 no ball u25 no ball v25 no ball w25 no ball y25 no ball u26 no ball v26 no ball w26 no ball y26 no ball u27 no ball v27 no ball w27 no ball y27 no ball u28 no ball v28 no ball w28 no ball y28 no ball u29 no ball v29 no ball w29 no ball y29 no ball u30 ov dd v30 gnd w30 gnd y30 v dd u31 pcireq1 v31 pcireq3 w31 pcireq5 y31 pcignt3 u32 gpio46* v32 gpio44* w32 pcireq4 y32 pcignt2 u33 gpio45* v33 pcireq2 w33 gnd y33 pcignt1 u34 gpio43* v34 pcireq0 /gnt w34 irq5* y34 pcignt0 /req table 6. signals listed by ba ll assignment (sheet 5 of 9) ball signal name ball signal name ball signal name ball signal name 440GRX ? ppc440GRX embedded processor preliminary data sheet 50 amcc proprietary revision 1.08 ? october 15, 2007 aa01 memdata53 ab01 memdata46 ac01 memdata41 ad01 gnd aa02 memdata52 ab02 memdata47 ac02 sov dd ad02 memdata44 aa03 memdata43 ab03 dm5 ac03 memdata40 ad03 memdata35 aa04 memdata42 ab04 dqs5 ac04 memdata45 ad04 memdata34 aa05 v dd ab05 v dd ac05 v dd ad05 v dd aa06 no ball ab06 no ball ac06 no ball ad06 no ball aa07 no ball ab07 no ball ac07 no ball ad07 no ball aa08 no ball ab08 no ball ac08 no ball ad08 no ball aa09 no ball ab09 no ball ac09 no ball ad09 no ball aa10 no ball ab10 no ball ac10 no ball ad10 no ball aa11 no ball ab11 no ball ac11 no ball ad11 no ball aa12 no ball ab12 no ball ac12 no ball ad12 no ball aa13 sov dd ab13 gnd ac13 no ball ad13 no ball aa14 gnd ab14 sov dd ac14 no ball ad14 no ball aa15 gnd ab15 gnd ac15 no ball ad15 no ball aa16 v dd ab16 v dd ac16 no ball ad16 no ball aa17 gnd ab17 gnd ac17 no ball ad17 no ball aa18 gnd ab18 gnd ac18 no ball ad18 no ball aa19 v dd ab19 v dd ac19 no ball ad19 no ball aa20 gnd ab20 gnd ac20 no ball ad20 no ball aa21 gnd ab21 eov dd ac21 no ball ad21 no ball aa22 eov dd ab22 gnd ac22 no ball ad22 no ball aa23 no ball ab23 no ball ac23 no ball ad23 no ball aa24 no ball ab24 no ball ac24 no ball ad24 no ball aa25 no ball ab25 no ball ac25 no ball ad25 no ball aa26 no ball ab26 no ball ac26 no ball ad26 no ball aa27 no ball ab27 no ball ac27 no ball ad27 no ball aa28 no ball ab28 no ball ac28 no ball ad28 no ball aa29 no ball ab29 no ball ac29 no ball ad29 no ball aa30 v dd ab30 v dd ac30 v dd ad30 v dd aa31 pcireset ab31 gpio23* ac31 gpio41* ad31 sysreset aa32 pciclk ab32 iic0sclk ac32 scpdi* ad32 syserr aa33 pcignt4 ab33 gpio26* ac33 eov dd ad33 gpio40* aa34 pcignt5 ab34 pciint ac34 scpclkout* ad34 gpio42* table 6. signals listed by ba ll assignment (sheet 6 of 9) ball signal name ball signal name ball signal name ball signal name 440GRX ? ppc440GRX embedded processor revision 1.08 ? october 15, 2007 amcc proprietary 51 preliminary data sheet ae01 memdata39 af01 memdata3 3 ag01 memodt1 ah01 banksel1 ae02 memdata38 af02 memdata37 ag02 gnd ah02 banksel0 ae03 dqs4 af03 memdata32 ag03 memdata36 ah03 memodt0 ae04 dm4 af04 sv ref2a ag04 memaddr13 ah04 cas ae05 gnd af05 sov dd ag05 gnd ah05 sov dd ae06 no ball af06 no ball ag06 no ball ah06 no ball ae07 no ball af07 no ball ag07 no ball ah07 no ball ae08 no ball af08 no ball ag08 no ball ah08 no ball ae09 no ball af09 no ball ag09 no ball ah09 no ball ae10 no ball af10 no ball ag10 no ball ah10 no ball ae11 no ball af11 no ball ag11 no ball ah11 no ball ae12 no ball af12 no ball ag12 no ball ah12 no ball ae13 no ball af13 no ball ag13 no ball ah13 no ball ae14 no ball af14 no ball ag14 no ball ah14 no ball ae15 no ball af15 no ball ag15 no ball ah15 no ball ae16 no ball af16 no ball ag16 no ball ah16 no ball ae17 no ball af17 no ball ag17 no ball ah17 no ball ae18 no ball af18 no ball ag18 no ball ah18 no ball ae19 no ball af19 no ball ag19 no ball ah19 no ball ae20 no ball af20 no ball ag20 no ball ah20 no ball ae21 no ball af21 no ball ag21 no ball ah21 no ball ae22 no ball af22 no ball ag22 no ball ah22 no ball ae23 no ball af23 no ball ag23 no ball ah23 no ball ae24 no ball af24 no ball ag24 no ball ah24 no ball ae25 no ball af25 no ball ag25 no ball ah25 no ball ae26 no ball af26 no ball ag26 no ball ah26 no ball ae27 no ball af27 no ball ag27 no ball ah27 no ball ae28 no ball af28 no ball ag28 no ball ah28 no ball ae29 no ball af29 no ball ag29 no ball ah29 no ball ae30 gnd af30 eov dd ag30 gnd ah30 eov dd ae31 gpio52* af31 gpio56* ag31 gpio58* ah31 gpio63* ae32 gpio50* af32 gpio55* ag32 trcclk ah32 gpio61* ae33 gpio51* af33 gpio54* ag33 gnd ah33 gpio59* ae34 gpio49* af34 gpio53* ag34 gpio57* ah34 gpio60* table 6. signals listed by ba ll assignment (sheet 7 of 9) ball signal name ball signal name ball signal name ball signal name 440GRX ? ppc440GRX embedded processor preliminary data sheet 52 amcc proprietary revision 1.08 ? october 15, 2007 aj01 gnd ak01 memclkout al01 memclkout am01 gnd aj02 we ak02 sov dd al02 memaddr10 am02 gnd aj03 ba0 ak03 ba1 al03 gnd am03 gnd aj04 ras ak04 gnd al04 gnd am04 gnd aj05 sov dd ak05 gnd al05 gnd am05 memaddr00 aj06 no ball ak06 sov dd al06 gnd am06 memaddr03 aj07 no ball ak07 sov dd al07 memaddr06 am07 memaddr08 aj08 no ball ak08 gnd al08 memaddr11 am08 memaddr12 aj09 no ball ak09 sov dd al09 ecc3 am09 ecc2 aj10 no ball ak10 gnd al10 sv ref1b am10 ecc6 aj11 no ball ak11 v dd al11 ecc1 am11 ecc0 aj12 no ball ak12 v dd al12 memdata27 am12 memdata31 aj13 no ball ak13 v dd al13 memdata30 am13 dqs3 aj14 no ball ak14 v dd al14 dm3 am14 memdata28 aj15 no ball ak15 v dd al15 memdata18 am15 memdata23 aj16 no ball ak16 gnd al16 dqs2 am16 memdata16 aj17 no ball ak17 gnd al17 memdata20 am17 memdata21 aj18 no ball ak18 sov dd al18 memdata09 am18 dm1 aj19 no ball ak19 gnd al19 sv ref2b am19 dqs1 aj20 no ball ak20 v dd al20 memdata03 am20 memdata02 aj21 no ball ak21 v dd al21 dm0 am21 dqs0 aj22 no ball ak22 v dd al22 memdata04 am22 memdata05 aj23 no ball ak23 v dd al23 gpio21* am23 gpio20* aj24 no ball ak24 v dd al24 gmctxd0* am24 gmctxer* aj25 no ball ak25 gnd al25 gpio25* am25 gpio24* aj26 no ball ak26 eov dd al26 gpio17* am26 gpio19* aj27 no ball ak27 gnd al27 gmctxclk* am27 gmcgtxclk* aj28 no ball ak28 eov dd al28 gmcrxd0* am28 gmcrxd2* aj29 no ball ak29 eov dd al29 gnd am29 gmcrxd4* aj30 eov dd ak30 gnd al30 gnd am30 gmcrxd7* aj31 gmcrxdv* ak31 gnd al31 gnd am31 gnd aj32 gmccd* ak32 gmccrs* al32 gnd am32 gnd aj33 gmcrefclk* ak33 eov dd al33 gmcrxer* am33 gnd aj34 gpio62* ak34 gmcmdio al34 gmcmdclk am34 gnd table 6. signals listed by ba ll assignment (sheet 8 of 9) ball signal name ball signal name ball signal name ball signal name 440GRX ? ppc440GRX embedded processor revision 1.08 ? october 15, 2007 amcc proprietary 53 preliminary data sheet an01 gnd ap01 gnd an02 gnd ap02 gnd an03 gnd ap03 gnd an04 gnd ap04 memaddr01 an05 sov dd ap05 memaddr02 an06 memaddr05 ap06 memaddr04 an07 memaddr07 ap07 memaddr09 an08 gnd ap08 ba2 an09 clken ap09 ecc7 an10 dm8 ap10 dqs8 an11 ecc5 ap11 ecc4 an12 sov dd ap12 memdata26 an13 memdata25 ap13 memdata24 an14 memdata29 ap14 memdata19 an15 memdata22 ap15 dm2 an16 gnd ap16 memdata17 an17 memdata10 ap17 memdata11 an18 memdata14 ap18 memdata15 an19 gnd ap19 memdata13 an20 memdata12 ap20 memdata08 an21 memdata06 ap21 memdata07 an22 memdata00 ap22 memdata01 an23 eov dd ap23 sysclk an24 gmctxen* ap24 av dd an25 gmctxd1* ap25 agnd an26 gpio18* ap26 gpio16* an27 gnd ap27 eagnd an28 gmcrxclk* ap28 eav dd an29 gmcrxd3* ap29 gmcrxd1* an30 eov dd ap30 gmcrxd5* an31 gnd ap31 gmcrxd6* an32 gnd ap32 gnd an33 gnd ap33 gnd an34 gnd ap34 gnd table 6. signals listed by ba ll assignment (sheet 9 of 9) ball signal name ball signal name ball signal name ball signal name 440GRX ? ppc440GRX embedded processor preliminary data sheet 54 amcc proprietary revision 1.08 ? october 15, 2007 signal descriptions the ppc440GRX embedded controller is packaged in a 456- ball enhanced plastic ball grid array (e-pbga). the following tables describe the package level pinout. in the table 9 on page 56, each i/o signal is listed along with a sh ort description of its function. active-low signals (for example, ras ) are marked with an overline. please see table 5 on page 19 for the pin (ball) number to which each signal is assigned. multiplexed signals some signals are multiplexed on the same pin so that the pin can be used for different functions. in most cases, the signal names shown in this table are not accompanied by signal names that may be multiplexed on the same pin. if you need to know what, if any, signals are mult iplexed with a particular signal, look up the name in table 5 on page 19. it is expected th at in any single applicatio n a particular pin will always be programmed to serve the same function. the flexibility of multiplexing allows a single chip to offer a richer pin selection than would otherwise be possible. note: signals multiplexed with gpio default to gpio receivers and float after reset. initializa tion software must configure the gpio registers for the desired function as described in th e gpio chapter of the user?s manual. any of these signals requiring a particular state prior to running initiali zation code must be terminated wit pull ups or pull downs . multipurpose signals in addition to multiplexing, some pins are also multi- purpose. for example, the ebc peripheral controller address pins (peraddr) are used as outputs by the ppc440GRX to broadcast an address to external slave devices when the ppc440GRX has control of the external bus. when during normal operation an external master gains ownership of the external bus, these same pins are used as inputs which are driven by the external master and received by the ebc in the ppc440GRX. in this example, the pins are also bidirectional, serving both as inputs and outputs. table 7. pin summary group no. of pins signal pins, non-multiplexed 268 signal pins, multiplexed 93 total signal pins 361 av dd 1 agnd 1 eav dd 1 eagnd 1 ov dd 30 sov dd 14 eov dd 12 v dd 56 gnd 197 total power pins 313 reserved 6 total pins 680 440GRX ? ppc440GRX embedded processor revision 1.08 ? october 15, 2007 amcc proprietary 55 preliminary data sheet multimode signals in some cases (for example, ethernet) the function of a pin may vary with different modes of operation. when a pin has multiple signal names assigned to distinguish different modes of operation, all of the names are shown. strapping pins one group of pins is used as strapped inputs during syst em reset. these pins function as strapped inputs only during reset and are used for other functions during no rmal operation (see ?strapping? on page 86). note that these are not multiplexed pins since the function of the pins is not programmable. reserved pins the pins classified as reserved are not functional and must be connected as shown in table 8. unused i/os termination of unused receivers is generally required ; however, there are some exceptions that reduce or eliminate the need for termination. signals multiplexed with gpio: by default after reset, signals shared with gpio pins ar e configured as gpio receivers. termination however, is not needed if the gpio during initialization are configur ed as outputs. to configure as drivers, set and clear the appropriate bits in the gpiox_odr, gpiox_tcr and gpiox_or registers as described in the gpio chapter of the user?s manual. pci: when the pci bridge is unused, conf igure the pci controller to park on the bus by pulling the pcireq0[gnt] signal low. parking forces the plb3 to pci bridge to actively drive pciad31:0 and pcic3:0[be3:0]. the remaining pci control signals must be terminated as follows: ? disable the internal pci arbiter and enable pci syc hronous mode (see iic boot strap chapter in the user?s manual). note: synchronous mode is not supported when operating the pci bus. this mode should only be used for terminating an unused pci interface). ? individually connect pciserr, pci perr, pcitrdy, and pcistop through 3k resistors to +3.3v. ? individually connect pcireq1:5 through 3k resistors to +3.3v. ? connect pcireq0[gnt] through 1k resistor to gnd. ddr: ? in 32 bit mode, termination is no t needed on the upper data, strobe and mask signals when the ddr i/o and ddr controller are configured for 32 bit mode, sdr0_ddrcfg[64b32b]=0 and ddr0_14[reduc=1. ? termination of unused ecc signals (e cc0:7, dm8, dqs8) is not needed. table 8. reserved pin connections pin connection a05 gnd j01 open j02 open l03 ov dd n02 gnd n03 gnd 440GRX ? ppc440GRX embedded processor preliminary data sheet 56 amcc proprietary revision 1.08 ? october 15, 2007 table 9. signal functional description (sheet 1 of 8) notes: 1. receiver input has hysteresis 2. must pull up (recommended value is 3k to ov dd (eov dd for ethernet) 3. must pull down (recommended value is 1k ) 4. if not used, must pull up (recommended value is 3k to ov dd (eov dd for ethernet) 5. if not used, must pull down (recommended value is 1k ) 6. strapping input during rese t; pull-up or pull-down required signal name description i/o type notes pci interface pciad00:31 address/data bus (bidirectional). i/o 3.3v pci pcic0:3/be0:3 pci command/byte enables . i/o 3.3v pci pciclk provides timing to the pci interf ace for pci transactions. i 3.3v pci 1, 5 pcidevsel indicates the driving device has decoded its address as the target of the current access. (pci 2.2 specification requires 8.2k pull up on host system). i/o 3.3v pci pciframe driven by the current master to indicate beginning and duration of an access. (pci 2.2 specification requires 8.2k pull up on host system). i/o 3.3v pci pcignt0 /req indicates that the specified agent is granted access to the bus. when the internal arbite r is enabled, output is pcignt0 . when the internal arbiter is disabled, output is req . o 3.3v pci pcignt1:5 indicates that the specified agent is granted access to the bus. used only when internal pci arbiter enabled. o 3.3v pci pciidsel used as a chip select during configuration read and write transactions. i 3.3v pci pciint level sensitive pci interrupt. o 3.3v pci pciirdy indicates initiating agent?s ability to complete the current data phase of the transaction. (pci 2.2 specification requires 8.2k pull up on host system). i/o 3.3v pci pcipar even parity. i/o 3.3v pci pciperr reports data parity errors during all pci transactions except a special cycle. (pci 2.2 specification requires 8.2k pull up on host system). i/o 3.3v pci pcireq0 /gnt indicates to the pci arbiter that the specified agent wishes to use the bus. when the internal arbiter is enabled, input is pcireq0 . when internal arbiter is disabled, input is gnt . i 3.3v pci 1, 4 pcireq1:5 an indication to the pci arbiter that the specified agent wishes to use the bus. used only when internal pci arbiter enabled. i 3.3v pci 1, 4 pcireset brings pci device registers and logic to a consistent state. o 3.3v pci pciserr reports address parity errors, data parity errors on the special cycle command, or other catastrophic system errors. (pci 2.2 specification requires 8.2k pull up on host system). i/o 3.3v pci pcistop indicates the current target is requesting the master to stop the current transaction. (pci 2.2 specification requires 8.2k pull up on host system). i/o 3.3v pci pcitrdy i ndicates the target agent?s ability to complete the current data phase of the transaction. (pci 2.2 specification requires 8.2k pull up on host system). i/o 3.3v pci 440GRX ? ppc440GRX embedded processor revision 1.08 ? october 15, 2007 amcc proprietary 57 preliminary data sheet ddr2/1 sdram interface ba0:2 bank address supporting up to eight internal banks. o 2.5v (1.8v) sdram-ddr banksel0:1 selects up to two external ddr sdram banks. o 2.5v (1.8v) sdram-ddr cas column address strobe. o 2.5v (1.8v) sdram-ddr clken clock enable. o 2.5v (1.8v) sdram-ddr dm0:7 dm8 memory write data byte lane masks. dm8 is the byte lane mask for the ecc byte lane. o 2.5v (1.8v) sdram-ddr dqs0:7 dqs8 byte lane data strobe. byte lane data strobe for ecc. i/o 2.5v (1.8v) sdram-ddr ecc0:7 ecc check bits 0:7. i/o 2.5v (1.8v) sdram-ddr memaddr00:13 memory address bus. o 2.5v (1.8v) sdram-ddr memdata00:63 memory data bus (memdata32:63 available for ddr2 only). i/o 2.5v (1.8v) sdram-ddr memclkout memclkout subsystem clock. o 2.5v (1.8v) sdram-ddr diff driver memodt0:1 ddr2 on-die termination enable (not used with ddr1). o 2.5v (1.8v) sdram-ddr ras row address strobe. o 2.5v (1.8v) sdram-ddr we write enable. o 2.5v (1.8v) sdram-ddr s vref1a:b ddr sdram reference voltage 1 input. i volt ref receiver (1.25v or 0.9v) s vref2a:b ddr sdram reference voltage 2 input. i volt ref driver (1.25v or 0.9v) table 9. signal functional description (sheet 2 of 8) notes: 1. receiver input has hysteresis 2. must pull up (recommended value is 3k to ov dd (eov dd for ethernet) 3. must pull down (recommended value is 1k ) 4. if not used, must pull up (recommended value is 3k to ov dd (eov dd for ethernet) 5. if not used, must pull down (recommended value is 1k ) 6. strapping input during rese t; pull-up or pull-down required signal name description i/o type notes 440GRX ? ppc440GRX embedded processor preliminary data sheet 58 amcc proprietary revision 1.08 ? october 15, 2007 ethernet interface gmcrxd0:1, gmc0rxd0:1, smii0:1rxd gmii/mii: receive data. rgmii 0: receive data. smii 0:1: receive data. i 3.3v tolerant 2.5v cmos 1 gmcrxd2:3, gmc0rxd2:3 gmii/mii: receive data. rgmii 0: receive data. i 3.3v tolerant 2.5v cmos 1 gmcrxd4:7, gmc1rxd0:3 gmii/mii: receive data. rgmii 1: receive data i 3.3v tolerant 2.5v cmos 1 gmctxd0:1, gmc0txd0:1, smii0:1txd gmii/mii: transmit data. rgmii 0: transmit data. smii 0:1: transmit data. o 3.3v tolerant 2.5v cmos gmctxd2:3, gmc0txd2:3 gmii/mii: transmit data. rgmii 0: transmit data. o 3.3v tolerant 2.5v cmos 1 gmctxd4:7, gmc1txd0:3 gmii/mii: transmit data. rgmii 1: transmit data. o 3.3v tolerant 2.5v cmos 1 gmcrxer, gmc1rxctl gmii/mii: receive error. rgmii 1: receive control. i 3.3v tolerant 2.5v cmos 1 gmcrxclk, gmc0rxclk, smiisync gmii/mii: receive clock. rgmii 0: receive clock. smii: synchronizing signal. i 3.3v tolerant 2.5v cmos 1, 5 gmcrxdv, gmc0rxctl gmii/mii: receive data valid. rgmii 0: receive control. i 3.3v tolerant 2.5v cmos 1 gmccrs, gmc1txclk gmii/mii: carrier sense. rgmii 0: transmit clock. i/o 3.3v tolerant 2.5v cmos 1 gmctxer, gmc1txctl gmii/mii: transmit error. rgmii 1: transmit control. o 3.3v tolerant 2.5v cmos gmctxen, gmc0txctl gmii/mii: transmit enable. rgmii 0: transmit control. o 3.3v tolerant 2.5v cmos gmctxclk mii: transmit clock for mii. o 3.3v tolerant 2.5v cmos 1, 5 gmccd, gmc1rxclk gmii/mii: collision detect. i 3.3v tolerant 2.5v cmos 1, 5 gmcmdclk management data clock o 3.3v tolerant 2.5v cmos gmcmdio management data i/o i/o 3.3v tolerant 2.5v cmos gmcgtxclk, gmc0txclk gmii: transmit clock for gmii. rgmii 0: transmit clock. o 3.3v tolerant 2.5v cmos gmcrefclk, smiirefclk gmii, rgmii: reference clock. smii: reference clock. i 3.3v tolerant 2.5v cmos rcvr 1, 5 rejectpkt0:1 external request to reject a packet. i 3.3v tolerant 2.5v cmos 1, 5 table 9. signal functional description (sheet 3 of 8) notes: 1. receiver input has hysteresis 2. must pull up (recommended value is 3k to ov dd (eov dd for ethernet) 3. must pull down (recommended value is 1k ) 4. if not used, must pull up (recommended value is 3k to ov dd (eov dd for ethernet) 5. if not used, must pull down (recommended value is 1k ) 6. strapping input during rese t; pull-up or pull-down required signal name description i/o type notes 440GRX ? ppc440GRX embedded processor revision 1.08 ? october 15, 2007 amcc proprietary 59 preliminary data sheet external slave peripheral interface dmaack0:3 used by the ppc440GRX to indicate that data transfers have occurred. o3.3v lvttl 1 dmareq0 used by slave peripherals to indicate they are prepared to transfer data. i 3.3v lvttl 1 dmareq1 used by slave peripherals to indicate they are prepared to transfer data. i 3.3vlvttl 1, 5 dmareq2:3 used by slave peripherals to indicate they are prepared to transfer data. i 3.3vlvttl 1 eot0:3/tc0:3 end of transfer/terminal count. i/o 3.3v lvttl 1 peraddr02:07 peripheral address bus used by the ppc440GRX when not in external master mode; otherwise, used by external master. i/o 3.3v lvttl 1, 2 peraddr08:31 peripheral address bus used by the ppc440GRX when not in external master mode; otherwise, used by external master. i/o 3.3v lvttl perdata00:31 peripheral data bus used by the ppc440GRX when not in external master mode; otherwise, used by external master. note: perdata00 is the most significant bit (msb) on this bus. i/o 3.3v lvttl perdatapar0:3 peripheral data bus parity used by the ppc440GRX when not in external master mode; otherwise, used by external master. i/o 3.3v lvttl perblast used by either the peripheral controller, dma controller, or external master to indicates the last transfer of a memory access. i/o 3.3v lvttl 1, 4 percs0 external peripheral devic e select. o 3.3v lvttl 2 percs1:5 external peripheral device select. i/o 3.3v lvttl 1, 2 peroe used by either peripheral controller or dma controller depending upon the type of transfer involved. when the ppc440GRX is the bus master, it enables the selected device to drive the bus. o 3.3v lvttl 1, 2 perready used by a peripheral slave to i ndicate it is ready to transfer data. i3.3v lvttl 1 perr/w used by the ppc440GRX when not in external master mode, as output by either the periphera l controller or dma controller depending upon the type of transfer involved. high indicates a read from memory, low indicates a write to memory. otherwise, it is used by the external master as an input to indicate the direction of transfer. i/o 3.3v lvttl 1, 2 perwbe0:3 external peripheral data bus by te enables. i/o 3.3v lvttl 1, 2 pererr external error. used as an input to record external slave peripheral errors. i3.3v lvttl 1 table 9. signal functional description (sheet 4 of 8) notes: 1. receiver input has hysteresis 2. must pull up (recommended value is 3k to ov dd (eov dd for ethernet) 3. must pull down (recommended value is 1k ) 4. if not used, must pull up (recommended value is 3k to ov dd (eov dd for ethernet) 5. if not used, must pull down (recommended value is 1k ) 6. strapping input during rese t; pull-up or pull-down required signal name description i/o type notes 440GRX ? ppc440GRX embedded processor preliminary data sheet 60 amcc proprietary revision 1.08 ? october 15, 2007 external master peripheral interface busreq bus request. used when the ppc440GRX needs to regain control of peripheral interface from an external master. o3.3v lvttl extack external acknowledgement. used by the ppc440GRX to indicate that a data transfer occurred. o3.3v lvttl extreq external request. used by an exter nal master to indicate it is prepared to transfer data. i3.3v lvttl 1 extreset peripheral reset. used by an external master and by synchronous peripheral slaves. note: the state of signals or clocks cannot be guaranteed until the extreset signal has been de-asserted. o3.3v lvttl holdack hold acknowledge. used by the ppc440GRX to transfer ownership of peripheral bus to an external master. o3.3v lvttl holdreq hold request. used by an external master to request ownership of the peripheral bus. i3.3v lvttl holdpri hold primary. used by an external master to indicate the priority of a given external master tenure. i 3.3v lvttl w/pull-up perclk peripheral clock. used by an external master and by synchronous peripheral slaves. o3.3v lvttl 1 uart peripheral interface the uart interface can be configured as follows: 1. one 8-pin, where n = 0 2. two 4-pin, where n = 0 & 1 3. one 4-pin, where n = 0 and two 2-pin, where n = 1 & 2 4. four 2-pin, where n = 0 & 1 & 2 & 3 uartserclk the serclk input provides an alternative to the internally generated serial clock. it is used in cases where the allowable internally generated clock rates are not satisfactory. i 3.3v lvttl 1, 4 uartn_rx receive data. i 3.3v lvttl rcvr 1, 4 uartn_tx transmit data. o 3.3v lvttl uartn_dcd data carrier detect. i 3.3v lvttl 1, 6 uartn_dsr data set ready. i 3.3v lvttl 1, 6 uartn_cts clear to send. i 3.3v lvttl 1, 6 uartn_dtr data terminal ready. o 3.3v lvttl 1 uartn_rts request to send. o 3.3v lvttl 1 uartn_ri ring indicator. i 3.3v lvttl 1 iic peripheral interface iic0sclk iic0 serial clock. i/o 3.3v lvttl 1, 2 iic0sdata iic0 serial data. i/o 3.3v lvttl 1, 2 iic1sclk iic1 serial clock. i/o 3.3v lvttl 1 iic1sdata iic1 serial data. i/o 3.3v lvttl table 9. signal functional description (sheet 5 of 8) notes: 1. receiver input has hysteresis 2. must pull up (recommended value is 3k to ov dd (eov dd for ethernet) 3. must pull down (recommended value is 1k ) 4. if not used, must pull up (recommended value is 3k to ov dd (eov dd for ethernet) 5. if not used, must pull down (recommended value is 1k ) 6. strapping input during rese t; pull-up or pull-down required signal name description i/o type notes 440GRX ? ppc440GRX embedded processor revision 1.08 ? october 15, 2007 amcc proprietary 61 preliminary data sheet nand flash interface nfale address latch enable. o 3.3v lvttl 1 nfce0:3 chip enable (multiplexed with the percs0:3 signals). o 3.3v lvttl 1 nfcle command latch enable. latches operational commands into the nand flash. o3.3v lvttl 1 nfrdybusy ready/busy . indicates status of device duri ng program erase or page read. this signal is wire-or connec ted from all nand flash devices. i3.3v lvttl 1 nfren read enable. data is latched on the rising edge. o3.3v lvttl 1 nfwen write enable. data is latched on the rising edge. o3.3v lvttl 1 serial peripheral interface scpclkout clock output. i/o 3.3v lvttl scpdi data input. i/o 3.3v lvttl scpdo data output. o 3.3v lvttl interrupts interface irq0:4 external interrupt requests 0 through 4. i/o 3.3v lvttl 1 irq5 external interrupt request 5. i 3.3v lvttl rcvr 1, 5 irq6:9 external interrupt requests 6 through 9. i/o 3.3v lvttl 1 jtag interface tck test clock. i 3.3v lvttl w/pull-up 1 tdi test data in. i 3.3v lvttl w/pull-up 1, 4 tdo test data out. o 3.3v lvttl tms test mode select. i 3.3v lvttl w/pull-up 1 trst test reset. i 3.3v lvttl w/pull-up 1, 5 table 9. signal functional description (sheet 6 of 8) notes: 1. receiver input has hysteresis 2. must pull up (recommended value is 3k to ov dd (eov dd for ethernet) 3. must pull down (recommended value is 1k ) 4. if not used, must pull up (recommended value is 3k to ov dd (eov dd for ethernet) 5. if not used, must pull down (recommended value is 1k ) 6. strapping input during rese t; pull-up or pull-down required signal name description i/o type notes 440GRX ? ppc440GRX embedded processor preliminary data sheet 62 amcc proprietary revision 1.08 ? october 15, 2007 system interface sysclk main system clock input. i 3.3v tolerant 2.5v cmos 1 syserr set to 1 when a machine check is generated. o 3.3v tolerant 2.5v cmos sysreset main system reset. external logi c can drive this bidirectional pin low (minimum of 16 cycles) to initiate a system reset. a system reset can also be initiated by software. implemented as an open-drain output (two states; 0 or open circuit). i/o 3.3v tolerant 2.5v cmos 1, 2 halt halt from external debugger. i 3.3v lvttl rcvr w/pull-up tmrclk processor timer external input clock. i 3.3v lvttl gpio00:15 gpio22:23 gpio26:48 general purpose i/o. to access these functions, software must set dcr register bits. i/o 3.3v lvttl 1 gpio16:21 gpio24:25 general purpose i/o. to access these functions, software must set dcr register bits. i/o 3.3v tolerant 2.5v cmos 1 gpio49:63 general purpose i/o. to access these functions, software must set dcr register bits. i/o 3.3v tolerant 2.5v cmos testen test enable. note: do not connect for normal operation. i 3.3v lvttl rcvr w/pull- down rcvrinh receiver inhibit. active only w hen testen is active. used for manufacturing test only. i3.3v lvttl 1 modectrl mode control. active only when testen is active. used for manufacturing test only. i 3.3v tolerant 2.5v cmos rcvr 1 leaktest leaktest2 leakage test. active only when testen is active. used for manufacturing test only. i 3.3v lvttl w/pull-up 1 refen reference enable. active only when testen is active. used for manufacturing test only. i3.3v lvttl 1 drvrinh1:2 driver inhibit. active only w hen testen is active. used for manufacturing test only. tie up as specified in note 2 for normal operation. i 3.3v lvttl w/pull-up 1 thermona:b on-chip pnp thermal monitor transistor. a is the emitter and b is the base. the collector is grounded. i thermal monitor 5 psroout module characterization and screening. use for test purposes only. tie down as specified in note 3 for normal operation. o perf screen ring osc 1, 3 table 9. signal functional description (sheet 7 of 8) notes: 1. receiver input has hysteresis 2. must pull up (recommended value is 3k to ov dd (eov dd for ethernet) 3. must pull down (recommended value is 1k ) 4. if not used, must pull up (recommended value is 3k to ov dd (eov dd for ethernet) 5. if not used, must pull down (recommended value is 1k ) 6. strapping input during rese t; pull-up or pull-down required signal name description i/o type notes 440GRX ? ppc440GRX embedded processor revision 1.08 ? october 15, 2007 amcc proprietary 63 preliminary data sheet trace interface trcbs0:2 trace branch execution status. i/o 3.3v tolerant 2.5v cmos trcclk trace data capture clock, runs at 1/4 the frequency of the processor. o 3.3v tolerant 2.5v cmos trces0:4 trace execution status is pr esented every fourth processor clock cycle. i/o 3.3v tolerant 2.5v cmos trcts0:6 additional information on trace execution and branch status. i/o 3.3v tolerant 2.5v cmos power v dd +1.5v?logic voltage. n/a n/a ov dd +3.3v?i/o (except ddr2 sdram and ethernet). n/a n/a eov dd +2.5v?i/o ethernet. n/a n/a sov dd +1.8v (ddr2) or +2.5v (ddr1)?i/o ddr sdram. n/a n/a gnd ground for logic and i/o voltage. n/a n/a av dd +1.5v?filtered voltage for system plls (analog). n/a n/a agnd ground for system pll voltage (analog). n/a n/a eav dd +1.5v?filtered voltage for ethernet plls (analog). n/a n/a eagnd ground for ethernet pll voltage (analog). n/a n/a reserved reserved to avoid noise pickup, the balls on this chip classified as reserved must be connected as shown in table 8 on page 55. na/ n/a table 9. signal functional description (sheet 8 of 8) notes: 1. receiver input has hysteresis 2. must pull up (recommended value is 3k to ov dd (eov dd for ethernet) 3. must pull down (recommended value is 1k ) 4. if not used, must pull up (recommended value is 3k to ov dd (eov dd for ethernet) 5. if not used, must pull down (recommended value is 1k ) 6. strapping input during rese t; pull-up or pull-down required signal name description i/o type notes 440GRX ? ppc440GRX embedded processor preliminary data sheet 64 amcc proprietary revision 1.08 ? october 15, 2007 device characteristics table 10. absolute maximum ratings the absolute maximum ratings bel ow are stress ratings only. operation at or beyond thes e maximum ratings can cause permanent damage to the device. none of the performance spec ification contained in this document are guaranteed when operating at these maximum ratings. characteristic symbol value unit notes internal logic supply voltage v dd 0 to +1.65 v 1 i/o supply voltage ov dd 0 to +3.6 v 1 ethernet i/o supply voltage eov dd 0 to +2.7 v 1 ddr2 (ddr1) sdram i/o supply voltage sov dd 0 to +1.94 (+2.7v) v 1 system analog supply voltage av dd 0 to +1.65 v ethernet analog supply voltage eav dd 0 to +1.65 v storage temperature range t stg ? 55 to +150 c case temperature under bias t c ? 40 to +120 c2 notes: 1. if ov dd 0.4v, it is required that v dd 0.4v. supply excursions not meeting this criter ia must be limited to less than 25ms duration during each power up or power down event. 2. this value is not a spec ification of the operational temperature range, it is a stress rating only. table 11. recommended dc operating conditions (sheet 1 of 2) device operation beyond the conditions specified is no t recommended. extended operation beyond the recommended conditions can affect device reliability. parameter symbol minimum typical maximum unit notes logic supply voltage v dd +1.425 +1.5 +1.6 v 4 i/o supply voltage ov dd +3.15 +3.3 +3.45 v 4 ethernet i/o supply voltage eov dd +2.4 +2.5 +2.6 v 4 ddr2 (ddr1) sdram i/o supply voltage sov dd +1.7 (+2.4) +1.8 (+2.5) +1.9 (+2.6) v 4 system analog supply voltages av dd +1.425 +1.5 +1.6 v 3, 4 ethernet analog voltage eav dd +1.425 +1.5 +1.6 v 3, 4 ddr2 (ddr1) sdram reference voltage sv ref +0.85 (+1.19) +0.9 (+1.25) +0.95 (+1.31) v 2 input logic high 3.3v pci v ih 0.5ov dd ov dd +0.5 v1 input logic high 3.3v lvttl +2.0 +3.6 v input logic high 2.5v cmos, 3.3v tolerant +1.7 +3.6 v input logic high 1.8v ddr2 (2.5v ddr1) sv ref + 0.125 (0.15) 2.2 (3.0) v 440GRX ? ppc440GRX embedded processor revision 1.08 ? october 15, 2007 amcc proprietary 65 preliminary data sheet input logic low 3.3v pci v il ? 0.5 0.35ov dd v1 input logic low 3.3v lvttl 0 +0.8 v input logic low 2.5v cmos 0 +0.7 v input logic low 1.8v ddr2 (2.5v ddr1) ? 0.3 ( ? 0.3) sv ref ? 0.125 (0.15) v output logic high 3.3v pci v oh 0.9ov dd -v1 output logic high 3.3v lvttl +2.4 +3.6 v output logic high 2.5v cmos +2.0 +2.7 v output logic high 1.8v ddr2 (2.5v ddr1) +0.95 (+1.7) +1.95 (+2.7) v 5 output logic low 3.3v pci v ol - 0.1ov dd v1 output logic low 3.3v lvttl 0 +0.4 v output logic low 2.5v cmos 0 +0.4 v output logic low 1.8v ddr2 (2.5v ddr1) 0 +0.43 (+0.54) v 5 input leakage current (no pull-up or pull-down) i il1 00 a input leakage current for pull-down i il2 0 (lpdl) 200 (mpul) a input leakage current for pull-up i il3 ? 150 (lpdl) 0 (mpul) a input max allowable overshoot 3.3v lvttl v imao +3.9 v input max allowable undershoot 3.3v lvttl v imau ? 0.6 v output max allowable overshoot 3.3v lvttl v omao +3.9 v output max allowable undershoot 3.3v lvttl v omau3 ? 0.6 v case temperature t c ? 40 +100 c6 notes: 1. pci drivers meet pci specifications. 2. sv ref = sov dd /2. sov dd = +1.8v for ddr2 memory or +2.5v for ddr1 memory. 3. the analog voltages used for the on-chip plls can be derived from the logic voltage, but must be filtered before entering the ppc440GRX. see ?absolute maximum ratings? on page 64. 4. startup sequencing of the power supply voltages is not required. a power-down cycle must complete (ov dd and v dd are below +0.4v) before a new power-up cycle is started 5. at i oh = i ol = 10ma. 6. case temperature, t c , is measured at top center of case surf ace with device soldered to a circuit board. table 11. recommended dc operating conditions (sheet 2 of 2) device operation beyond the conditions specified is no t recommended. extended operation beyond the recommended conditions can affect device reliability. parameter symbol minimum typical maximum unit notes 440GRX ? ppc440GRX embedded processor preliminary data sheet 66 amcc proprietary revision 1.08 ? october 15, 2007 figure 4. overshoot waveform table 12. input capacitance parameter symbol maximum unit notes 2.5v/1.8v ddr c in1 2.9 pf 3.3v lvttl c in2 2.1 pf pci c in3 2.5 pf 3.3v tolerant cmos c in5 2.4 pf table 13. overshoot and undershoot receiver ac overshoot (v) dc overshoot (v) dc undershoot (v) ac undershoot (v) t os 3.3v lvttl 3.9 3.6 -0.16 -0.6 0.1*t cyc 1 2.5v (3.3v tolerant) 3.9 3.6 -0.16 -0.6 0.1*t cyc 1 ddr 1.2*sov dd sov dd + 0.3 -0.3 -0.6 0.1/memclkout pci 1.2*ov dd ov dd + 0.5 -0.5 -0.2*ov dd 0.1/pciclk notes: 1. t cyc is the period of the bus clock. 1/perclk - ebc and nand flash interfaces. 1/gmcrxclk - gmii and mii modes 1/smiirefclk - smii mode 1/gmcgrxclk - rgmii mode 1/trcclk - instruction trace interface 1/iic0clk and 1/iic1clk - iic interfaces 1/spiclkout - spi ac undershoot (v) t os t os dc overshoot (v) dc undershoot (v) t cyc ac overshoot (v) 440GRX ? ppc440GRX embedded processor revision 1.08 ? october 15, 2007 amcc proprietary 67 preliminary data sheet power sequencing startup sequencing of the power supply voltages is not required. however, a power-down cycl e must complete (ov dd and v dd are below +0.4v) before a new power-up cycle is started. analog voltage filter the analog voltages (avdd and eavdd) used for the on-chip plls ca n be derived from the logic voltage, but must be filtered before entering the ppc440GRX. a separate filter, as shown below, is recommended for each voltage. ? the filter should keep the analog voltage to analog ground compression/expansion due to noise less than +/- 50 mv. ? keep all wire lengths as short as possible. ? analog grounds must be brought out and connected to the digital ground plane at the filter capacitor. ? the impedance of the ferrite bead should be much greater th an that of the capacitor at frequencies where noise is expected. table 14. typical dc power supply requirements using ddr2 memory frequency (mhz) +1.5v supply (v dd +av dd +eav dd ) +1.8v supply (sov dd ) +2.5v supply (eov dd ) +3.3v supply (ov dd +uav dd ) total unit notes 400 1.35 0.9 0.2 0.7 3.15 w 1 533 1.45 0.9 0.2 0.7 3.25 w 1 667 1.9 0.9 0.2 0.7 3.7 w 1 notes: 1. typical power is estimated and is based on a nominal voltage of v dd = +1.5v, t c = 85 c, while running linux and a test application that exercises each functiion wi th representative traffic. table 15. typical dc power supply requirements using ddr1 memory frequency (mhz) +1.5v supply (v dd +av dd +eav dd ) +1.8v supply (sov dd ) +2.5v supply (sov dd + eov dd ) +3.3v supply (ov dd +uav dd ) total unit notes 400 1.35 na 1.3 0.7 3.35 w 1 533 1.45 na 1.3 0.7 3.45 w 1 667 1.9 na 1.3 0.7 3.9 w 1 notes: 1. typical power is estimated and is based on a nominal voltage of v dd = +1.5v, t c = 85 c, while running linux and a test application that exercises each functiion wi th representative traffic. v dd c av dd, sav dd l l ? smt ferrite bead chip, murata blm21pg600sn1 c ? 0.1 f ceramic agnd, sagnd gnd 440GRX ? ppc440GRX embedded processor preliminary data sheet 68 amcc proprietary revision 1.08 ? october 15, 2007 table 16. v dd supply power dissipation frequency (mhz) +1.425v +1.5v +1.6v unit notes 400 1.2 1.35 1.55 w 1 533 1.25 1.45 1.7 w 1 667 1.7 1.9 2.4 w 1 notes: 1. power is estimated and is based on v dd specified in the table and t c = 85 c, while running linux and a te st application that exercises each function with representative traffic. table 17. dc power supply loads parameter symbol typical maximum unit notes v dd (+1.5v) active operating current i dd 1600 2900 ma ov dd (+3.3v) active operating current i odd 160 260 ma eov dd (+2.5v) active operating current i eodd 80 100 ma sov dd (+1.8v) ddr2 active operating current 2 i sodd2 500 600 ma sov dd (+2.5v) ddr1 active operating current 2 i sodd1 400 500 ma av dd (+1.5v) input current i add 20 30 ma 1 eav dd (+1.5v) active operating current i eadd 20 30 ma 1 notes: 1. 1. see ?absolute maximum ratings? on page 64 for filter recommendations. 2. 2. sov dd will be either +2.5v or +1.8v, but not both. 3. the maximum current values listed above are not guaranteed to be the highest obtainable. these values are dependent on many factors including the type of applications r unning, clock rates, use of internal func tional capabilities, external interface us age, case temperature, and the power supply voltages . your specific application can produc e significantly different results. v dd (logic) current and power are primarily dependent on the applicatio ns running and the use of internal chip functions (dma, pci, ethernet, and so on ). ov dd (i/o) current and power are primarily dependent on the capaciti ve loading, frequency, and utilizat ion of the external buses. 4. typical current is estimated at 667mhz with v dd = +1.5v, ov dd = +3.3v, eov dd = +2.5v, sov dd = +2.5v (ddr1) or +1.8v (ddr2), and t c = +85c. 5. maximum current is estimated at 667mhz with v dd = +1.6v, ov dd = +3.45v, eov dd = +2.6v, sov dd = +2.6v (ddr1) or +1.9v (ddr2), and tc = +100c, and best-case pr ocess (which drives worst-case power). 440GRX ? ppc440GRX embedded processor revision 1.08 ? october 15, 2007 amcc proprietary 69 preliminary data sheet thermal management the following heat sink was used in the above thermal analysis: alpha lpd35-15b (35mm x 35mm x15mm) the heat sink is manufactured by: alpha novatech, inc. (www.alphanovatech.com) 473 sapena court, #12 santa clara, ca 95054 phone: 408-567-8082 table 18. package thermal specifications thermal resistance values for the te-pbga package in a convection environment at 6.3w are as follows: parameter symbol airflow ft/min (m/sec) unit notes 0 (0) 100 (0.51) 200 (1.02) 300 (1.53 400 (2.04) 500 (2.55) junction-to-ambient thermal resistance without heat sink ja 13.1 11.7 10.9 10.5 10.3 10 c/w 5 junction-to-ambient thermal resistance with heat sink ja 11.1 8.2 7.2 6.8 6.6 6.3 c/w 5, 6 resistance value junction-to-case thermal resistance jc 3.5 c/w 5 junction-to-board thermal resistance jb 7.3 c/w 5 notes: 1. case temperature, t c , is measured at top center of case su rface with device soldered to circuit board. 2. t a = t c ? p ca , where t a is ambient temperature and p is power consumption. 3. t cmax = t jmax ? p jc , where t jmax is maximum junction temperature (+ 125c) and p is power consumption. 4. the preceding equations assume that the chip is mount ed on a board with at least one signal and two power planes. 5. values in the table were achieved using a jedec standard board with the following characteristics: 114.5mm x 101.6mm x 1.6mm, 4 layers. the board has 100 thermal vias (same as th e number of thermal balls on the te-pbga package). 6. values for an attached heat sink were achieved with a 35mm x 35mm x 15mm unit (see thermal management below), attached with a 0.1mm thickness of adhesive having a thermal conductivity of 1.3w/mk. 440GRX ? ppc440GRX embedded processor preliminary data sheet 70 amcc proprietary revision 1.08 ? october 15, 2007 thermal monitor thermal monitoring of the chip is accomplished using the pnp transistor ( 2) provided on the chip. the collector of the transistor is connected to ground (gnd). the emitter (thermona) and base (thermonb) are connected to chip pins. a voltage measurement (v be1 and v be2 ) across the thermona and thermonb pins at the two current values i 1 and i 2 provides the chip temperature in k according to the equation: t = (q/nk)(v be2 ? v be1 )/ln(i 2 /i 1 ) k where q = 1.602 176 5310 -19 , n = 1.0 0.015, and k = 1.380 650510 -23 . note: v be2 and v be1 should be specified in volts. i 1 and i 2 can be any units of measure provided they are the same. the small values require precision measurement and current sources. test conditions clock timing and switching characteristics ar e specified in accordance with operating conditions shown in the table table 11 on page 64. ac specifications are characterized with v dd =+1.5v, t c = +85 c and a 50pf test load as shown in the figure to the right. thermona thermonb ppc440GRX i 1 , i 2 (max = 300 a) e b v be1 , v be2 note: the bias voltage v eb should be between +0.5v and +0.7v. c output pin 50pf 440GRX ? ppc440GRX embedded processor revision 1.08 ? october 15, 2007 amcc proprietary 71 preliminary data sheet figure 5. timing waveform note: sysclk and gmcrefclk are 2.5v (3.3v tolerant). sl ew rate should be measur ed between 0.7v and 1.7v. table 19. clocking specifications symbol parameter min max units notes sysclk input f c frequency 33.33 66.66 mhz t c period 15 30 ns t cs edge stability (cycle-to-cycle jitter) ? 0.15 ns t ch high time 40% of nominal period 60% of nominal period ns t cl low time 40% of nominal period 60% of nominal period ns note: input slew rate 1v/ns pll vco f c frequency 600 1333.33 mhz t c period 0.750 1.66 ns processor (cpu) clock f c frequency 333.33 666.66 mhz 1 t c period 1.5 3 ns memclkout and plb clock f c frequency 133.33 166.66 mhz t c period 6 7.5 ns t ch high time 45% of nominal period 55% of nominal period ns mal clock f c frequency 45 83.33 mhz t c period 12 22.2 ns notes: 1. the maximum supported processor clock fr equency for any part is specified in the part number (see ?ordering and pvr informati on? on page 5). t cl t ch t c 1.7v (2.0v) 0.7v (0.8v) 440GRX ? ppc440GRX embedded processor preliminary data sheet 72 amcc proprietary revision 1.08 ? october 15, 2007 spread spectrum clocking care must be taken when using a spread spectrum cloc k generator (sscg) with the ppc440GRX. this controller uses a pll for clock generation inside the chip. the accura cy with which the pll follows the sscg is referred to as tracking skew. the pll bandwidth and phase angle determine how much tracking skew there is between the sscg and the pll for a given frequency deviation and modulation frequency. when using an sscg with the ppc440GRX the following conditions must be met: ? the frequency deviation must not violate the minimum clock cycle time. therefore, when operating the ppc440GRX with one or more internal clocks at their ma ximum supported frequency, the sscg can only lower the frequency. ? the maximum frequency de viation cannot exceed ? 3%, and the modulation frequency cannot exceed 40khz. in some cases, on-board ppc440GRX peripher als impose more stringent requirements. ? use the peripheral bus clock for logic that is synchron ous to the peripheral bus since this clock tracks the modulation. ? use the ddr sdram memclkout sinc e it also tracks the modulation. notes: 1. the serial port baud rates are synchronous to the modulated clock. the serial port has a tolerance of approximately 1.5% on baud rate before framing errors begin to occur. the 1.5% tolerance assumes that the connected device is runni ng at precise baud rates. 2. ethernet operation is unaffected. 3. iic operation is unaffected. important: it is up to the system designer to ensure t hat any sscg used with the ppc 440GRX meets the above requirements and does not adversely affect other aspects of the system. 440GRX ? ppc440GRX embedded processor revision 1.08 ? october 15, 2007 amcc proprietary 73 preliminary data sheet i/o specifications table 20. peripheral interface clock timings parameter min max units notes pciclk frequency (asynchronous mode) ? 66.66 mhz pciclk period (asynchronous mode) 15 ? ns pciclk high time 40% of nominal period 60% of nominal period ns pciclk low time 40% of nominal period 60% of nominal period ns gmcmdclk frequency ? 2.5 mhz gmcmdclk period 400 ? ns gmcmdclk high time 160 ? ns gmcmdclk low time 160 ? ns gmctxclk frequency mii 2.5 25 mhz gmctxclk period mii 40 400 ns gmctxclk high time 35% of nominal period ? ns gmctxclk low time 35% of nominal period ? ns gmcrxclk frequency mii 2.5 25 mhz gmcrxclk period mii 40 400 ns gmcrxclk high time 35% of nominal period ? ns gmcrxclk low time 35% of nominal period ? ns gmcrefclk frequency ? 125 mhz gmcrefclk period 8 ? mhz gmcrefclk high time 40% of nominal period 60% of nominal period ns 2 gmcrefclk low time 40% of nominal period 60% of nominal period ns 2 perclk (and opb clock) frequency (for ext. master or sync. slaves) 33.33mhz 83.33 mhz gmcrefclk edge stability (cycle-to-cycle jitter) ? + 0.15 ns gmcrefclk slew rate 2 ? v/ns perclk period 12 30 ns perclk high time 50% of nominal period 66% of nominal period ns perclk low time 33% of nominal period 50% of nominal period ns uartserclk frequency ? 1000 / (2t opb 1 +2ns) mhz 1 uartserclk period 2t opb 1 +2 ?ns1 uartserclk high time t opb 1 +1 ?ns1 uartserclk low time t opb 1 +1 ?ns1 440GRX ? ppc440GRX embedded processor preliminary data sheet 74 amcc proprietary revision 1.08 ? october 15, 2007 figure 6. input setup and hold waveform figure 7. output delay and float timing waveform tmrclk frequency ? 100 mhz tmrclk period 10 ? ns tmrclk high time 40% of nominal period 60% of nominal period ns tmrclk low time 40% of nominal period 60% of nominal period ns notes: 1. t opb is the period in ns of the opb clock. t he internal opb clock runs at 1/2 the frequenc y of the plb clock. the maximum opb clock frequency is 83 mhz. 2. an internal pll improves th is duty cycle to a worst case of 48% minimum, 52% maximum. table 20. peripheral interface clock timings (continued) parameter min max units notes clock t is t ih min min inputs valid 1.25v(1.5v) valid clock outputs valid t oh min t ov max t ov max t oh min t ov max t oh min float (high-z) high (drive) low (drive) 1.25v(1.5v) 440GRX ? ppc440GRX embedded processor revision 1.08 ? october 15, 2007 amcc proprietary 75 preliminary data sheet figure 8. input setup and ho ld waveform for rgmii signals figure 9. output delay and hold timing waveform for rgmii signals t is t ih min min inputs valid valid t is t ih min min 1.25v rgmii 1000mb timing is with reference to the ra ising and falling edge of gmcnrxclk. rgmii 10/100mb timing is with reference on ly to the raising edge of gmcnrxclk. gmcnrxclk valid gmcntxclk outputs t oh min t ov max float (high-z) high (drive) low (drive) valid valid valid t oh min t ov max 1.25v rgmii 1000mb timing is with reference to the ra ising and falling e dge of gmcntxclk. rgmii 10/100mb timing is with reference on ly to the raising edge of gmcntxclk. 440GRX ? ppc440GRX embedded processor preliminary data sheet 76 amcc proprietary revision 1.08 ? october 15, 2007 table 21. i/o specifications?all speeds (sheet 1 of 3) notes: 1. ethernet interface meets timing requirem ents as defined by ieee 802.3 standard. signal input (ns) output (ns) output current (ma) clock notes setup time (t is min) hold time (t ih min) valid delay (t ov max) hold time (t oh min) i/o h (minimum) i/o l (minimum) pci interface pciad31:00 3 0 6 2 0.5 1.5 pciclk pcic3:0/be3:0 3 0 6 2 0.5 1.5 pciclk pciclk n/a n/a async pcidevsel 5 0 6 2 0.5 1.5 pciclk pciframe 5 0 6 2 0.5 1.5 pciclk pcignt0:5 n/a n/a 6 2 0.5 1.5 pciclk pciidsel 5 0 n/a n/a n/a n/a pciclk pciint n/a n/a n/a n/a 0.5 1.5 async pciirdy 5 0 6 2 0.5 1.5 pciclk pcipar 5 0 6 2 0.5 1.5 pciclk pciperr 5 0 6 2 0.5 1.5 pciclk pcireq0:5 5 0 n/a n/a n/a n/a pciclk pcireset n/a n/a n/a n/a n/a n/a async pciserr 5 0 6 2 0.5 1.5 pciclk pcistop 5 0 6 2 0.5 1.5 pciclk pcitrdy 5 0 6 2 0.5 1.5 pciclk ethernet mii interface gmccd n/a n/a n/a n/a 5.1 6.8 async gmccrs n/a n/a n/a n/a 5.1 6.8 async gmcmdclk 5.1 6.8 gmcmdio 10 10 10 1.5 5.1 6.8 gmcmdclk gmcrxclk n/a n/a gmcrxd0:3 10 10 n/a n/a 5.1 6.8 gmcrxclk gmctxd0:3 n/a n/a 10 1 5.1 6.8 gmctxclk gmcrxdv 10 10 n/a n/a 5.1 6.8 gmcrxclk gmcrxer 10 10 n/a n/a 5.1 6.8 gmcrxclk gmctxclk n/a n/a gmctxer n/a n/a 10 1 5.1 6.8 gmctxclk gmctxen n/a n/a 10 1 5.1 6.8 gmctxclk ethernet gmii interface gmccd n/a n/a n/a n/a 5.1 6.8 async gmccrs n/a n/a n/a n/a 5.1 6.8 async gmcgtxclk 5.1 6.8 gmcmdclk 5.1 6.8 gmcmdio 10 10 10 1.5 5.1 6.8 gmcmdclk gmcrefclk n/a n/a gmcrxclk 5.1 6.8 gmcrxd0:7 2 0 n/a n/a 5.1 6.8 gmcrxclk gmctxd0:7 n/a n/a 2.5 1 5.1 6.8 gmcgtxclk gmcrxdv 2 0 n/a n/a 5.1 6.8 gmcrxclk gmcrxer 2 0 n/a n/a 5.1 6.8 gmcrxclk gmctxer n/a n/a 2.5 1 5.1 6.8 gmcgtxclk gmctxen n/a n/a 2.5 1 5.1 6.8 gmcgtxclk 440GRX ? ppc440GRX embedded processor revision 1.08 ? october 15, 2007 amcc proprietary 77 preliminary data sheet ethernet rgmii interface gmc0rxclk n/a n/a gmc0txclk 5.1 6.8 gmc0rxd0:3 1 1 n/a n/a 5.1 6.8 gmc0rxclk gmc0rxctl 1 1 n/a n/a 5.1 6.8 gmc0rxclk gmc0txd0:3 n/a n/a 0.5 3.5 5.1 6.8 gmc0txclk gmc0txctl n/a n/a 0.5 3.5 5.1 6.8 gmc0txclk gmc1rxclk n/a n/a gmc1txclk 5.1 6.8 gmc1rxd0:3 1 1 n/a n/a 5.1 6.8 gmc1rxclk gmc1rxctl 1 1 n/a n/a 5.1 6.8 gmc1rxclk gmc1txd0:3 n/a n/a 0.5 3.5 5.1 6.8 gmc1txclk gmc1txctl n/a n/a 0.5 3.5 5.1 6.8 gmc1txclk gmcrefclk n/a n/a ethernet smii interface smiirefclk n/a n/a smiisync na na 3 1 5.1 6.8 smiirefclk smii0rxd 1.5 1 n/a n/a 5.1 6.8 smiirefclk smii1rxd 1.5 1 n/a n/a 5.1 6.8 smiirefclk smii0txd n/a n/a 3 1 5.1 6.8 smiirefclk smii1txd n/a n/a 3 1 5.1 6.8 smiirefclk internal peripheral interface iic0sclk 27.7 12.8 iic0sdata n/a n/a 5 0 27.7 12.8 iic1sclk 27.7 12.8 iic1sdata n/a n/a 5 0 27.7 12.8 scpclkout 27.7 12.8 scpdi 5 1.5 n/a n/a 27.7 12.8 scpdo n/a n/a 6 0 15.3 10.2 uartserclk n/a n/a uartn_rx n/a n/a n/a n/a n/a n/a uartn_tx n/a n/a n/a n/a 19.1 8.7 uartn_dcd n/a n/a n/a n/a n/a n/a uartn_dsr n/a n/a n/a n/a n/a n/a uartn_cts n/a n/a n/a n/a n/a n/a uartn_dtr n/a n/a n/a n/a 19.1 8.7 uartn_ri n/a n/a n/a n/a n/a n/a uartn_rts n/a n/a n/a n/a 19.1 8.7 interrupts interface irq0:9 n/a n/a n/a n/a n/a n/a jtag interface tck n/a n/a n/a n/a n/a n/a async tdi n/a n/a n/a n/a n/a n/a async tdo n/a n/a n/a n/a 19.1 8.7 async tms n/a n/a n/a n/a n/a n/a async trst n/a n/a n/a n/a n/a n/a async table 21. i/o specifications?all speeds (sheet 2 of 3) notes: 1. ethernet interface meets timing requirem ents as defined by ieee 802.3 standard. signal input (ns) output (ns) output current (ma) clock notes setup time (t is min) hold time (t ih min) valid delay (t ov max) hold time (t oh min) i/o h (minimum) i/o l (minimum) 440GRX ? ppc440GRX embedded processor preliminary data sheet 78 amcc proprietary revision 1.08 ? october 15, 2007 system interface sysclk n/a n/a tmrclk n/a n/a async sysreset n/a n/a n/a n/a n/a n/a async halt n/a n/a n/a n/a n/a n/a async syserr n/a n/a n/a n/a 5.1 6.8 async testen n/a n/a n/a n/a n/a n/a async drvrinh1:2 n/a n/a n/a n/a n/a n/a rcvrinh n/a n/a n/a n/a n/a n/a gpio00:11 n/a n/a n/a n/a 19.1 8.7 gpio12:25 n/a n/a n/a n/a 5.1 6.8 gpio26:48 n/a n/a n/a n/a 14.6 6.6 gpio49:63 n/a n/a n/a n/a 5.1 6.8 trace interface trcclk n/a 5.1 6.8 trcbs0:2 n/a n/a n/a n/a 5.1 6.8 trces0:4 n/a n/a n/a n/a 5.1 6.8 trcts0:6 n/a n/a n/a n/a 5.1 6.8 table 21. i/o specifications?all speeds (sheet 3 of 3) notes: 1. ethernet interface meets timing requirem ents as defined by ieee 802.3 standard. signal input (ns) output (ns) output current (ma) clock notes setup time (t is min) hold time (t ih min) valid delay (t ov max) hold time (t oh min) i/o h (minimum) i/o l (minimum) 440GRX ? ppc440GRX embedded processor revision 1.08 ? october 15, 2007 amcc proprietary 79 preliminary data sheet table 22. i/o specifications?400mhz to 667mhz notes: 1. perclk rising edge at package pin with a 10pf load tr ails the internal plb clock by approximately 1.3ns. signal input (ns) output (ns) output current (ma) clock notes setup time (t is min) hold time (t ih min) valid delay (t ov max) hold time (t oh min) i/o h (minimum) i/o l (minimum) external slave peripheral interface dmaack0:3 n/a n/a 6 1 19.1 8.7 perclk dmareq0:3 4 1 n/a n/a n/a n/a perclk eot0:3/tc0:3 4 1 6 1 19.1 8.7 perclk peraddr02:31 4 1 6 1 19.1 8.7 perclk perblast 4 1 6 1 19.1 8.7 perclk percs0:5 n/a n/a 6 1 19.1 8.7 perclk perdata00:15 4 1 6 1 19.1 8.7 perclk perdata16:31 4 1 6 1 14.6 6.6 perclk peroe n/a n/a 6 1 19.1 8.7 perclk perready 4 1 n/a n/a 19.1 8.7 perclk perr/w 4 1 6 1 19.1 8.7 perclk perwbe0:1 4 1 6 1 19.1 8.7 perclk external master peripheral interface busreq n/a n/a 6 1 19.1 8.7 perclk extack n/a n/a 6 1 19.1 8.7 perclk extreq 4 1 n/a n/a 19.1 8.7 perclk extreset n/a n/a 6 1 19.1 8.7 perclk holdack n/a n/a 6 1 19.1 8.7 perclk holdreq 4 1 n/a n/a n/a n/a perclk holdpri 4 1 n/a n/a n/a n/a perclk 19.1 8.7 plb clk 1 pererr 4 1 n/a n/a n/a n/a perclk nand flash interface nfale n/a n/a 6 1 19.1 8.7 perclk nfce0:3 n/a n/a 6 1 19.1 8.7 perclk nfcle n/a n/a 6 1 19.1 8.7 perclk nfrdybusy 4 1 n/a n/a n/a n/a perclk nfren n/a n/a 6 1 19.1 8.7 perclk nfwen n/a n/a 6 1 19.1 8.7 perclk 440GRX ? ppc440GRX embedded processor preliminary data sheet 80 amcc proprietary revision 1.08 ? october 15, 2007 ddr2/1 sdram i/ o specifications the ddr2/1 sdram controller times it s operation with the internal plb cl ock signal and generates memclkout from the plb clock. the plb clock is an internal signal that cannot be directly observed. however memclkout is the same frequency as the plb clock signal and is in phase with the plb clock signal. read capture logic in the ddr controller captures read data using a de layed version of dqs and internally re- synchronizes the data to the plb clock.the ppc440GRX co ntains three independently programmable digital delay lines (dlls) that control the timing of the in dicated signals in read and write operations: 1. dqs (with respect to mem clkout) for write operations. 2. memdata, ecc, and dm (with respec t to memclkout) fo r write operations. 3. dqs (with respect to inbound memdata) for read operations. there is also a master delay line for calibra tion. programming details can be found in the ppc440GRX embedded processor users manual . the signals are terminated as indicated in figure 10 for the ddr timing data in the following sections. the ppc440GRX uses a clock forwarding scheme in which it drives the clock to the memory devices. data signals are divided into eight subgroups?one for each byte lane (see table 27 on page 85)? plus a ninth subgroup for the ecc byte lane. these signals includ e memdata00:63, dqs0:8, dm0:8, and ecc0:7 signals. signals within a data subgroup (byte lane) should be routed together. command bus operation the command bus (memaddr, ras , cas , we , ba, clken, banksel, me modt) is driven 180 out-of-phase with memclkout, and has no corresponding delay line. therefore, board designers must consider two different types of systems: 1) registered dimms and 2) unbuffered dimms. th e system clocking design must also be considered. to avoid crosstalk, the command bus signals and the data signals should not be routed together. board layout restrictions the paths (traces) for the data and the associated data strobe signal should be routed with the same length between the ppc440GRX and the sdram dev ices, allowing the rising and falling edg es of the strobe to arrive at the capture logic at the same time the da ta is in transition. all of the following timing assumes a trace velocity of 167ps/in. board designs must meet the following criteria: ? skew on the signals in any byte lane should not exceed 50ps (0.3 in). ? data subgroup trace lengths must be no more than 5in. (800ps) and have a difference of no more than 2.5in. (400ps). ? byte lane subgroup trace length must be no less than 1.25 in. (209ps). for example, traces that average 3.00in. in length a nd 167ps/in., and meet the maximum 50ps skew requirement, would have a maximum length difference of 0.3in. so, they would be between 2.85in. and 3.15in. in length. if the above timing recommendations are followed, the package wire bond lengths can be ignored. clocking clocking skew to all drams must be minimized. the maximum allowed is considered to be 10ps. because of the stringent requiremen ts on ddr device clock inputs, it is expe cted that board designers will use some type of external pll suitable to redrive the clock to the ddr sd rams. in such a system, the pll acts like a zero-delay insertion buffer. 440GRX ? ppc440GRX embedded processor revision 1.08 ? october 15, 2007 amcc proprietary 81 preliminary data sheet when using unbufferred dimms, the loading on the addre ss bus will be considerably greater than the clock (up to 18 loads for double-sided dimms). in this case, it is strong ly suggested that a delay of 500ps in the clock path so that the address/command setup time at the dimms can be met. this delay is sufficient to meet the setup time, without having to change the programmable delay (internal to the ppc440GRX) between the dqs/dq/dm and the clock (assuming nominal settings as specified in the ppc 440GRX users manual). while the clock is now 500ps later than the nominal dqs arrival ti me, this still falls well within the wind ow allowed by the jedec spec for t dqss ( 0.25 cycle, or 1.5ns at 166mhz). in the case where it is not possible to anticipate which kind of dimms may be employed in a system, it is always safe to use this 50 0ps clock delay, since registered dimms (the least heavily loaded) will have more th an enough margin (almost 1/2 cyc le) to accommodate the slight decrease in address hold time. termination model figure 10. ddr sdram simulation signal termination model ddr2 sdram on-die termination impedance setting for all ddr2 applications, the on-die termination (odt) impedance value must be set to 75 ohms in the dimm extended mode register (emr) in order to optimize th e data transmission during memory write operations. table 23. ddr sdram output driver specifications (sheet 1 of 2) signal path output current (ma) i/o h (maximum) i/o l (maximum) write data memdata00:63 10 10 ecc0:7 10 10 dm0:8 10 10 memclkout 10 10 memaddr00:13 10 10 ba0:2 10 10 10pf 10pf memclkout memclkout 120 50 30pf addr/ctrl/data/dqs/dm (ddr1) v tt = sov dd /2 ppc440GRX addr/ctrl (ddr2) note: this diagram illustrates the model of the ddr sdram interface used when generating simulation timing data. it is not a recommended physical circuit design for this interface. an actual interface design will depend on many factors, including the type of memory used and the board layout. 440GRX ? ppc440GRX embedded processor preliminary data sheet 82 amcc proprietary revision 1.08 ? october 15, 2007 ddr sdram write operation the rising edge of memclkout aligns with the first rising edge of the dqs signal on writes. the following data is generated by means of simulation and includes logic, dr iver, package rlc, and lengths. values are calculated over best case and worst case pr ocesses with speed, junction temperature, and voltage as follows: note: in the following tables and timing diagrams, minimum values are measured under best case conditions and maximum values are measured under worst case conditio ns. the timing numbers in the following sections are obtained using a simulation that assumes a model as shown in figure 10, ddr sdram simulation signal termination model . ras 10 10 cas 10 10 we 10 10 banksel0:1 10 10 clken 10 10 dqs0:8 10 10 memodt0:1 10 10 table 24. ddr sdram write operation conditions case process speed junction temperature (c) voltage (v) best fast ? 40 +1.6 worst slow +125 +1.425 table 23. ddr sdram output driver specifications (sheet 2 of 2) signal path output current (ma) i/o h (maximum) i/o l (maximum) 440GRX ? ppc440GRX embedded processor revision 1.08 ? october 15, 2007 amcc proprietary 83 preliminary data sheet the following diagram illustrates the relationship among the signals in volved with a ddr write operation. figure 11. ddr sdram write cycle timing note: the timing data in the following tables is based on simulation runs using einstimer. dqs memdata plb clk memclkout addr/cmd t sk t sa t ha t ds t ds t sd t hd t sd t hd t sa = setup time for address and command signals to memclkout t sk = delay from falling edge of memclkout to rising/falling edge of signal (skew) t ha = hold time for address and command signals from memclkout t ds = delay from rising/falling edge of clock to the rising/falling edge of dqs t sd = setup time for data signals (minimum time data is valid before rising/falling edge of dsq) t hd = hold time for data signals (minimum time data is valid after rising/falling edge of dsq) 440GRX ? ppc440GRX embedded processor preliminary data sheet 84 amcc proprietary revision 1.08 ? october 15, 2007 table 25. i/o timing?ddr sdram t ds notes: 1. all of the dqs signals are re ferenced to memclkout with the dqs delay line programmed to 1 cycle. 2. clock speed is 166mhz. signal name t ds (ns) minimum maximum dqs0 ? 0.030 + 0 . 650 dqs1 ? 0.030 + 0 . 620 dqs2 ? 0.050 + 0 . 580 dqs3 ? 0.110 + 0 . 480 dqs4 ? 0.140 + 0 . 410 dqs5 ? 0.120 + 0 . 480 dqs6 ? 0.060 + 0 . 580 dqs7 ? 0.010 + 0 . 690 dqs8 ? 0.140 + 0 . 420 table 26. i/o timing?ddr sdram t sk , t sa , and t ha notes: 1. clock speed is 166mhz. t sk is referenced to memclkout falling edge. t sa and t ha are referenced to memclkout rising edge. 2. the timing in this table assumes a single registered dimm load on the outputs. to adjust t he timing for unbuffered dimms, use the following values by subtracting them from t sa and adding them to t sk and t ha : 5 loads adjust by 0.41ns 9 loads adjust by 1.12ns 18 loads adjust by 2.12ns 3. to obtain adjusted t sa values for lower clock frequencies, use 1/2 of the cy cle time for the lower clock frequency and subtract t sk maximum (0.5t cyc ? t sk max). 4. to obtain adjusted t ha values for lower clock frequencies, use 1/2 of the cycle time for the lower clock frequency and add t sk minimum (0.5t cyc + t sk min). signal name t sk (ns) t sa (ns) t ha (ns) minimummaximumminimum minimum memaddr00:13 ? 0.960 ? 0.270 3.27 2.04 ba0:2 banksel0:1 clken cas ras we 440GRX ? ppc440GRX embedded processor revision 1.08 ? october 15, 2007 amcc proprietary 85 preliminary data sheet ddr sdram read operation the read data capture logic is responsi ble for capturing the data outputs fr om the sdram devices and passing the data back to the system clock domain. the data strobe si gnal (dqs) signals used to capture data are delayed to ensure that the rising and falling edges of these strobes are in the middle of the valid window of data. ddr devices send a dqs coincident with the read data so that the data can be reliably captured by the ppc440GRX. the edges of these str obe signals are aligned with the da ta output by the sdram devices. i n order to reliably latch the data into a synchronizing fifo, the ppc440GRX produces an internal, delayed version of dqs. the amount of delay is user programmable. in the example shown in figure 12, ddr sdram dqs read timing , the delay is set to approximately 25% of the system clock. a delay compensation circuit in the ppc440GRX keeps this delay constant. figure 12. ddr sdram dqs read timing table 27. i/o timing?ddr sdram t sd and t hd notes: 1. t sd and t hd are measured under worst case conditions. 2. clock speed for the values in the table is 166mhz. 3. the time values in the table include 1/ 4 of a cycle at 166mhz (6ns x 0.25 = 1.5 ns). 4. to obtain adjusted t sd and t hd values for lower clock frequencies, subtract 1. 5 ns from the values in the table and add 1/4 of the cycle time for the lower clock frequency (for example, t sd ? 1.5 + 0.25t cyc ). signal names reference signal t sd (ns) t hd (ns) memdata00:07, dm0 dqs0 1.37 1.23 memdata08:15, dm1 dqs1 1.41 1.18 memdata16:23, dm2 dqs2 1.40 1.17 memdata24:31, dm3 dqs3 1.41 1.20 memdata32:39, dm4 dqs4 1.45 1.18 memdata40:47, dm5 dqs5 1.40 1.18 memdata48:55, dm6 dqs6 1.46 1.17 memdata56:63, dm7 dqs7 1.45 1.10 ecc0:7, dm8 dqs8 1.46 1.18 dqs delay memclkout dqs memdata delayed dqs (data strobe) 440GRX ? ppc440GRX embedded processor preliminary data sheet 86 amcc proprietary revision 1.08 ? october 15, 2007 initialization the ppc440GRX provides the option for setting initial parame ters based on default values or by reading them from a slave prom attached to the iic0 bus (see ?serial eeprom? be low). some of the default values can be altered by strapping on external pins (see ?strapping? below). strapping while the sysreset input pin is low (system reset), the state of cert ain i/o pins is read to enable certain default initial conditions prior to ppc440GRX start-up. the actual capture instant is the nearest reference clock edge before the deassertion of reset. these pins must be strapped using external pull-up (logical 1) or pull-down (logical 0) resistors to select the desired default condit ions. these pins are used for strap functions only during reset. following reset they are used for normal functions. the signal names assigned to the pins for normal operation are shown in parentheses following the pin number. note: when uart0_dcd , uart0_dsr and uart0_cts are used functionally, the pin straps should be isolated from the uart transceiver during re set as the transceiver may overdrive the pin straps and cause the ppc440GRX to read incorrect straps. the following table lists the strapping pins al ong with their functions and strapping options: serial eeprom during reset, initial conditions other than those obtained from the strapping pins can be read from a rom device connected to the iic0 port. at the de-assertion of reset, if the boots trap controller is enabled, the ppc440GRX sequentially reads 16b from the rom device on the iic0 port and sets the sdr0_sdstp0, sdr0_sdstp1, sdr0_sdstp2 and sdr0_sdstp3 registers accordingly. the initialization settings and their default values are covered in detail in the powerpc 440GRX user?s manual . table 28. strapping pin assignments function option pin strapping c28 (uart0_dcd ) c29 (uart0_dsr ) a29 (uart0_cts ) serial device is disabled. ea ch of the six options (a? f) is a combination of boot source, boot-source width, and clock frequency specifications. refer to the iic bootstrap controller chapter in the ppc440GRX embedded processor user?s manual for details. a 000 b 001 c 010 d 011 e 100 f 110 serial device is enabled. the option being selected is the iic0 slave address that will respond with strapping data. g (0xa8)101 h (0xa4)111 440GRX ? ppc440GRX embedded processor revision 1.08 ? october 15, 2007 amcc proprietary 87 preliminary data sheet revision log date version contents of modification 04/11/2006 1.01 initial creation of document. 04/24/2006 1.02 correct security designation. add new/updated power and current values. 05/30/2006 1.03 correct list containi ng balls by ball number. update power and temperature data. add clocking information. update eeprom. 11/02/2006 1.04 change and delete incorrect memclken references correct enable/disable specificat ions for pci gnt/req signals. change analog voltage filter circuit inductor part number. correct i/o designation for some ethernet signals. remove leaded pns. 12/28/2006 1.05 correct descriptions of leaktest, rcvrinh, modectrl, refen, and drvrinh1:2 signals. add information concerning addr ess bus loading on ddr sdrams. restore leaded pns. 01/10/2007 1.06 update ddr2/1 sdram timing and board design data. 07/25/2007 1.07 added more information to the thermal monitor section. changes to figure 3. 10/15/2007 1.08 added assembly recommendations, tables 3 and 4. added recommendations for unused i/o. updated signal description in table 9for si gnals spcclkout, scpdi, scpdo, leaktest and leaktest2. updated table 21 to include reference clocks. removed all references to tbi and rtbi as these modes are not supported due to errata: chip_4 and chip_5. added voltage reference to figures 5, 6 and 7 corrected i/o comments for uart and ethernet signals in table 9. removed note 2 from table 10and added section on analog voltage filter added figure 4 and table 13 for overshoot and undershoot. added section on power sequencing. added slew rate and jitter requirements for gmcrefclk in table 20. added note in strapping section changed gpio26[iic0sdata] to [gpio26]iic0sdata in table 9. added figures 8 and 9 showing setup, hold, out put valid and output hold timing for rgmii signals. corrected pvr number corrected phone numbers on last page corrected rgmii timing relative to gmcntxclk in table 21. added pull up recommendations to table 9 for pci signals. 440GRX ? ppc440GRX embedded processor preliminary data sheet 88 amcc proprietary revision 1.08 ? october 15, 2007 applied micro circuits corporation 215 moffett park drive, sunnyvale, ca 94089 phone: (408) 542-8600 ? (800) 840-6055 ? fax: (408) 542-8601 http://www.amcc.com amcc reserves the right to make changes to its products, its data sheets, or related documentation, without notice and warrants its products solely pursuant to its terms and conditions of sale, only to substantially co mply with the latest availab le data sheet. please consult amcc?s term and c onditions of sale for its warranties and other terms, conditions and limitations. amcc may discontinue any semiconductor product or service wi thout notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orde rs, that the information is current. amcc does not assume any liability arising out of the application or use of any product or circuit described herein, nei ther does it convey any license under its patent rights nor the rights of others. amcc reserves the right to ship devices of higher grade in place of those of lower grade. amcc semiconductor products are not designed , intended, authorized, or warranted to be suitable for use in life-support applications, devices or systems or other critical applications. amcc is a registered trademark of appli ed micro circuits corporation. copyright ? 2006 applied micro circuits corporation. all rights reserved. |
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